Renesas Electronics Corporation

Nissan Motor Company Limited

Amada Company, Limited

Sony Semiconductor Solutions Corporation

Fuji Xerox Co., Ltd.

Shiseido Company, Limited

Anritsu Corporation

Keio University

Piolax, Inc.

Takashi Matsumoto

Hiroyuki Kobayashi

Hiroshi Nakai

Shigeru Endo

Masayuki Shimizu

Kinshiro Naito

Toshio Kumamoto

Takashi Okuda

Kiyoshi Natori

Masao Ito

Isao Watanabe

Osamu Matsumoto

Masaki Fujiwara

Yasuo Morimoto

Takashi Moue

Yoshikazu Soyama

Kenzo Ito

Hiroto Suzuki

Hajime Matsuda

Takashi Minami

Noriko Tomita

Akio Nasu

Takayuki Miyazaki

Yohei Hamano

Hiroaki Ichioka

Hideyuki Sumiyoshi

Tomoaki Koi

Yoshihiro Shiozawa

Kosuke Tomita

Naohito Okude

Taketoshi Kamada

Yutaka Kamoshita

Marie Goto

A load control device includes a device that has a plurality of operation modes depending on applications and is electrically connected to a load. The device includes an operation mode determination circuit. The operation mode determination circuit is configured to: set a tentative operation mode indicating the operation mode before determination; obtain operation mode information regarding the operation mode via communication, the operation mode information including an error detection code for detecting an error of the tentative operation mode; determine whether or not a setting result of the tentative operation mode is correct using the error detection code; and determine the operation mode of the device based on a determination result.

Load control device, load control system, and load control method

A relay device includes a relay connected between a first communication network and a second communication network. The second communication network uses a communication protocol different from the first communication network. A first frame is transmitted in the first communication network, and has a first payload including control information, a first data ID for identifying the control information, and a data length code indicating a data length of the first payload. A second frame is transmitted in the second communication network, and has the first frame, a second data ID indicating that the first frame is included, and unique data stored in a predetermined storage area at a position behind the first frame. The relay recognizes the first frame without performing a frame recognition process on the data in the predetermined storage area when recognizing the first frame in the second frame on a basis of the data length code.

Relay device, communication network system, and communication control method

A CGW () connected to a first communication network () and a fifth communication network (). The second communication network uses a communication protocol different from a communication protocol of the first communication network (). The CGW () receives, from the first communication network (), CAN frames each including a data field storing control information (CD) to be transmitted from the first communication network () to a second communication network (), a CAN ID for identifying the control information (CD), and an error detection code (EC) stored in the data field and calculated on the basis of the control information (CD) and the CAN ID. The CGW () generates an FD frame including a data field storing the CAN frames and a CAN FD ID indicating that the CAN frames are stored in the data field, and transmits the generated FD frame to the fifth communication network ().

Instability of an internal state in a current-input-type delta-sigma modulator is reduced in a case where input changes sharply. A signal current is input to a first integration node. A difference current between a fixed current and the signal current is input to a second integration node. A voltage-to-current converter that converts a difference voltage between the voltage of the first integration node and a first reference voltage into a current and outputs it is connected between the first integration node and the second integration node. The voltage of the second integration node is compared with a second reference voltage, and a 1-bit digital signal is output. Current is draws from the first integration node or the second integration node according to the 1-bit digital signal. A short-circuit switch is provided between the first integration node and the second integration node for short-circuiting them.

Delta-sigma modulator and method of driving delta-sigma modulator

Included are a loop filter, a quantization circuit section, and a current steering digital-analog conversion section. The quantization circuit section converts a loop filter output into a digital value. The current steering digital-analog conversion section is provided in a feedback loop that feeds back the output of the quantization circuit section to the loop filter. Then, each of the analog-digital converters includes a first input signal current path, a second input signal current path, a first feedback current path, and a second feedback current path. The first input signal current path feeds a first input signal current to an input end of a first stage integrator of the loop filter. The second input signal current path feeds a second input signal current, a current opposite in sign to the first input signal current, to an input end of a second stage integrator of the loop filter. The first feedback current path connects one feedback output end of the current steering digital-analog conversion section to the input end of the first stage integrator of the loop filter. The second feedback current path connects other feedback output end of the current steering digital-analog conversion section to the input end of the second stage integrator of the loop filter.

Analog-digital converter, solid-state imaging element, and electronic equipment

To provide a semiconductor device capable of accurately controlling the cycle of an internal clock signal. This semiconductor device, by using signal that is output from a sequence register of an asynchronous successive approximation type ADC when N times of comparison are completed, detects whether or not the signal and its delay signal are output when the period transitions from a comparison period to a sampling period, and generates, on the basis of the detection result, a delay control signal for controlling the cycle of an internal clock signal by controlling the delay times of the delay circuits.

Semiconductor device

A die body includes a die hole for punching a work. A core, including a discharge hole, which is in communication with the die hole, is provided in the die body. The core is provided with a plurality of fluid injection ports through which fluid is injected downward of the discharge hole. The die body is provided with inflow ports through which compressed fluid flows into the fluid injection ports. The core is made of resin. The discharge hole is tapered toward its upper side. An outer peripheral surface of the die body is provided with a peripheral groove which is in communication with the inflow ports.

Die and die device

A delta-sigma A/D converter having plural input channels comprises a first quantizer which quantizes and outputs a received signal; a first D/A converter which converts an output signal of the first quantizer into an analog signal, and outputs the converted analog signal; a first operation unit which outputs a signal indicative of a difference of the first analog input signal and an output signal of the first D/A converter; a first integrator which integrates an output signal of the first operation unit and outputs the integrated signal; a first dither circuit which generates a first dither signal; and a second operation unit which adds the first dither signal to the output signal of the first integrator and outputs the added signal to the first quantizer.

Delta-sigma A/D converter

To provide a technique for simplifying a parameter setting process required to generate a test signal based on an LTE-Advanced system. Carrier arrangement designation meansdisplays a screen for selecting one of an intra-band type or an inter-band type as the arrangement of a plurality of component carriers used in an LTE-Advanced system such that one of the intra-band type or the inter-band type is designated. Parameter file designation meansdesignates a parameter file to be allocated to the component carrier among test signal generating parameter files stored in a parameter file storage meansParameter and frequency band allocation meansdesignates the component carrier to which the designated parameter file can be allocated and the allocated frequency band for communication in which the component carriers are arranged.

Test signal generation apparatus and method based on LTE-advanced system

A successive approximation register A/D converter that obtains an output of N bits interrupts operation at a timing when the operation of the successive approximation register A/D converter is affected on the basis of circuit timing in an integrated circuit. The A/D converter performs a comparison between a sampling signal and a comparison reference voltage by a sampling period in which an analog signal is sampled, a comparison period of N states in which the sampled signal is sequentially compared with a comparison voltage for each bit, and a reserve period of M states following the comparison period. When an operation is temporarily interrupted, the A/D converter performs a comparison operation of a bit, whereas the comparison is not performed in the reserve period.

Integrated circuit

A mesa photodiode which includes a mesa, the side wall of the mesa (a light-receiving region mesa) and at least a shoulder portion of the mesa in an upper face of the mesa are continuously covered with a semiconductor layer of a first conductivity type, a second conductivity type, a semi-insulating type, or an undoped type (an undoped InP layer, for example) that is grown on the side wall and the upper face of the mesa. In the semiconductor layer, a layer thickness Dof a portion covering the side wall of the mesa is equal to or greater than 850 nm.

Mesa photodiode and method for manufacturing the same

In a delta-sigma A/D converter provided with plural channels for converting an analog input signal into a digital signal, an adverse influence of an idle tone is reduced in each channel. The delta-sigma A/D converter comprises: a first quantizer which quantizes and outputs a received signal; a first D/A converter which converts an output signal of the first quantizer into an analog signal, and outputs the converted analog signal; a first operation unit which outputs a signal indicative of a difference of the first analog input signal and an output signal of the first D/A converter; a first integrator which integrates an output signal of the first operation unit and outputs the integrated signal; a first dither circuit which generates a first dither signal; and a second operation unit which adds the first dither signal to the output signal of the first integrator and outputs the added signal to the first quantizer.

A first LCD&#x2dc;a sixth LCDare disposed on each surface of a display apparatus which becomes a cubic shape in its entirety. With image data to be displayed on the LCDs, correlated is a position of a surface to be displayed, of the cubic, and in accordance with the correlated surface position, it is transferred to at least one of the display data output sections. A control sectionoutputs a control signalwhich controls a correlation of image data and the LCDswhich display an image based upon the image data, by utilizing information which shows this surface position and a up/down direction from a up/down detection section. A changeover switchconnects, in accordance with the control signal, the display data output sectionsand drive circuitswhich drive the LCDsat corresponding positions.

Display apparatus

Growing community of inventors

Kanagawa, Japan

Takashi Matsumoto