Seiko Epson Corporation

Kabushiki Kaisha Toshiba

Takashi Makino

Seiji Kimura

Ayumu Nakamura

Tsukasa Abe

Tomoko Iwasaki

Hiroto Miyauchi

Kenichi Hirabayashi

Ichiro Yoshioka

Soichiro Kii

Genta Kawabe

Katsuyuki Endo

Yusuke Yamashita

Tomohisa Kano

Etsuo Tsuji

Shinichiro Yoshikawa

Shinsuke Tomomatsu

Yoriko Hama

Makoto Hoshina

Shuji Asami

Makoto Terashima

Mikio Goto

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Tap arithmetic units and first delay circuits are arranged alternately. Each of the tap arithmetic units has a full-adder array for multiplying an input signal which has been sampled at regular intervals and coefficients, a second pipeline delay circuit for delaying outputs of the full-adder array by a predetermined time and an adder circuit for adding outputs of the second delay circuits. The first and second delay circuits are timed to the preceding tap arithmetic unit for arithmetic operations. The use of the second delay circuit for the timing of arithmetic operations permits the arrangement of the first delay circuit to be simplified.

Input-weighted transversal filter

A selector sequentially selects different coefficients during a time interval T. A plurality of coefficient multipliers multiply an input signal sampled at intervals T and coefficients selected by the selector. An input circuit selects, at interval T/2, an input signal supplied at intervals T. A pipeline type adder adds an output signal of the input circuit and output signals of the coefficient multipliers. An output circuit adds an output signal of the adder in an interval of T/2 and outputs the result of the addition as a signal of a period of T.

A delay circuit comprising a plurality of clocked inverters coupled cascade form. Each clocked inverter includes a plurality of MOS FETs. The circuit further comprises delay time-controlling MOS FETs connected in parallel to the MOS FETs of the clocked inverters, which are controlled by clock signals. When the delay time-controlling MOS FETs are turned on, the clocked inverters function as ordinary inverters. Conversely, when the delay time-controlling MOS FETs are turned off, the clocked inverters perform their own functions. Hence, one of two different delay times can be selected.

Delay circuit of a variable delay time

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Matsumoto, Japan

Takashi Makino