Kabushiki Kaisha Toshiba

Kioxia Corporation

Mitsubishi Electric Corporation

Toyota Jidosha Kabushiki Kaisha

Denso Corporation

Brother Kogyo Kabushiki-kaisha

Mitsubishi Denki Kabushiki Kaisha

Toshiba Memory Corporation

Hoya Corporation

Fujitsu Corporation

Nsk Corporation

Nippon Steel & Sumitomo Metal Corporation

Jx Nippon Oil Energy Corporation

National Institute of Advanced Industrial Science and Technology

Kabushiki Kaisha Daini Seikosha

Takashi Maeda

Takanori Matsunaga

Toshinori Matsui

Yoshihisa Iwata

Hiroshi Fujioka

Yohei Masui

Rieko Funatsuki

Hideyuki Tanaka

Masahiko Kurishige

Hidehiro Shiga

Tomoya Sanuki

Hiroshi Maejima

Keisuke Nakatsuka

Kazutaka Ikegami

Yuji Hamada

Takeshi Nishiwaki

Takayoshi Takehara

Naoki Kusumoto

Yuki Tezuka

Hideaki Aochi

Masumi Saitoh

Takeshi Nanami

Minoru Nakadori

Tadashi Sakai

Takatoshi Tosa

Yoshiaki Adachi

Takeshi Furukido

Takeo Kawamata

Hiroyuki Kimura

Keisuke Morita

Takanori Tsunashima

Mitsuhiro Tokimasa

Toshio Fujisawa

Hiroyuki Nakayama

Yuji Igarashi

Tomoo Hishida

Masahiko Ikawa

Kiyotaro Itagaki

Hisashi Sugawara

Kouji Kitsunai

Ryo Mizuno

Yoshinori Osakabe

Hiroyasu Tanaka

Masaru Kito

Ryota Katsumata

Masaru Kidoh

Tsuneo Inaba

Akihiro Nitayama

Tetsuaki Utsumi

Hiroyuki Yamaguchi

Toshifumi Hashimoto

Hideki Isono

Shinji Eda

Shuichi Kubota

Muneaki Takahata

Shigeki Morita

Go Shikata

Hiroshi Shibazaki

Tsunekazu Yasoshima

Hiroshi Tsuchiya

Mitsuharu Yonemura

Masayoshi Oosaki

Hiroyuki Matsuzaki

Yoshinori Marumo

Reika Tanaka

Keiji Nakajima

Yuta Kojima

Katsuya Kawai

Tadashi Murase

Takashi Suzuki

Hajime Sato

Yoshihiro Ueda

Kenji Tsuchida

Hiroshi Araki

Yasuhito Yoshimizu

Kenichiro Yoshii

Satoshi Matsumoto

Takayuki Miyazaki

Masayuki Sato

Takashi Kumagai

Masayuki Miura

Takahiko Hara

Yukio Goto

Masaki Fujii

Masuo Ito

Mie Matsuo

Makoto Adachi

Kazuhiko Adachi

Shingo Nakazawa

Hideo Wada

Sumiko Domae

Hideto Horii

Hiroshi Kawachi

Yuichiro Ito

Yoshihito Ono

Ichiro Kotani

Kazuumi Kondo

Masayuki Shibuya

Minoru Ogawa

Naoyuki Nakamura

According to one embodiment, in a semiconductor memory device, a gate electrode of a first PMOS transistor and a gate electrode of a first NMOS transistor are commonly connected, and a first contact plug is connected to the commonly-connected gate electrodes to at least partly overlap with an isolation portion when viewed in a third direction perpendicular to a first direction and a second direction. A gate electrode of a second PMOS transistor and a gate electrode of a second NMOS transistor are commonly connected, and a second contact plug is connected to the commonly-connected gate electrodes to at least partly overlap with the isolation portion when viewed in the third direction.

Semiconductor memory device

A memory system according to an embodiment includes a first bit line, a source line, a first word line, a second word line, a first memory pillar and a control circuit. The control circuit performs a first verify operation to first and second memory cells, a second verify operation to the first memory cell, a third verify operation to the second memory cell and a write operation or a read operation with a lower voltage in accordance with a request from an external device.

Memory system with verify operations of odd and even word lines

A control circuit of a semiconductor memory device performs a write operation on a memory cell transistor of the semiconductor memory device by performing a first pulse application operation of lowering a threshold voltage of the memory cell transistor, a precharge operation, and then a second pulse application operation. In the precharge operation, in a state in which first and second select transistors connected to the memory cell transistor are turned on, a bit line connected to the memory cell transistor is charged by applying a ground voltage to a word line connected to a gate of the memory cell transistor and applying a voltage higher than the ground voltage to a source line. In the second pulse application operation, in a state in which the first select transistor is turned on and the second select transistor is turned off, a program voltage is applied to the word line.

A semiconductor memory device includes a first memory pillar and a sequencer. The first memory pillar is sandwiched between a first word line and a second word line, sandwiched between a third word line and a fourth word line, sandwiched between a fifth word line and a sixth word line, includes a first memory cell facing the first word line, a second memory cell facing the second word line, a third memory cell facing the third word line, a fourth memory cell facing the fourth word line, a fifth memory cell facing the fifth word line and a sixth memory cell facing the sixth word line. The sequencer executes an erase operation on the first to sixth memory cells to enable execution of a primary write operation for the first memory cell and a primary write operation for the second memory cell at different timings.

A semiconductor memory device includes a semiconductor pillar including first and second memory cells electrically connected in series and formed on opposite sides of the semiconductor pillar, first word lines connected to the first memory cells, respectively, and second word lines connected to the second memory cells, respectively. A verify operation includes a channel clean operation for supplying a reference voltage to a semiconductor channel shared by the first and second memory cells followed by at least first and second sense operation for determining whether a threshold voltage of a target memory cell has reached first and second threshold voltage states, respectively, then a second channel clean operation for supplying the reference voltage to the semiconductor channel, and then at least a third sense operation for determining whether the threshold voltage of the target memory cell has reached a third threshold voltage state.

A semiconductor memory device includes a driver that, in a write operation, applies a first voltage to a first select gate line, applies a second voltage lower than the first voltage to a second select gate line, applies a third voltage equal to or higher than the first voltage to a first dummy word line on an uppermost layer, applies a fourth voltage different from the third voltage and higher than the second voltage to a second dummy word line on an uppermost layer, applies a fifth voltage equal to or higher than the third voltage to a first dummy word line on a lowermost layer, and applies a sixth voltage different from the fifth voltage and equal to or higher than the fourth voltage to a second dummy word line on a lowermost layer.

A device for setting a target vehicle that sets a target vehicle to be subjected to driving assistance control of a host vehicle includes: a detection signal acquisition device capable of acquiring a first detection signal representing an object by an image, and a second detection signal representing the object by a reflection point; and setting control unit, which determines whether to set a forward object as a target vehicle, wherein if a movement history is not associated with the forward object, and a combination history is associated with the forward object, then as a selection threshold of a first determination parameter for determining whether to set the forward object as the target vehicle, a selection threshold is used such that the forward object is less likely to be selected as the target vehicle than with the selection threshold which would be used if a movement history is associated with the forward object.

Device for setting target vehicle, system for setting target vehicle, and method for setting target vehicle

When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Nonvolatile semiconductor memory device

A semiconductor memory device includes i first word lines connected to the i first memory cells, i second word lines connected to the i second memory cells, a driver capable of supplying voltage to each of the i first word lines and each of the i second word lines, and a logic control circuit controlling both a write operation including a verify operation and a read operation including a verify operation. In the semiconductor memory device, when an order of performing a sense operation for determining whether or not a threshold voltage of the k-th first memory cell has reached a j-th threshold voltage in the verify operation is different from that of in the read operation, a voltage applied to the k-th first word line in the verify operation is different from a voltage applied to the k-th first word line in the read operation.

A reading device includes a reading sensor, a platen on which a first original and a second original being longer in a first direction can be placed, and a controller. the controller moves the reading sensor from an initial position to a standby position, causes the reading sensor to detect edges of the original while moving by a predetermined distance in the first direction, detect edges of the original while moving toward the initial position when a first edge in the first direction and a second edge in a second direction orthogonal to the first direction are detected or when neither of the edges are detected, detect edges while moving in a direction away from the initial position when the first edge is not detected and the second edge is detected, and acquire a content of the original while moving toward the initial position when the first edge is detected.

Reading device, reading method, and computer-readable recording medium

A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.

Semiconductor memory device having transistors between bonding pads and word lines

A memory system has a memory cell array having a plurality of strings, the plurality of strings each having a plurality of memory cells connected in series, and a controller configured to perform control of transferring charges to be stored in the plurality of memory cells in the string or transferring charges according to stored data, between potential wells of channels in the plurality of memory cells.

Memory system

An object is to share information of detected obstacles on a road among communication devices, using efficient communication. A communication device according to the present disclosure includes: a wireless receiving unit for receiving wireless information including first obstacle information of a first obstacle which is at least one obstacle, from outside; a first obstacle extraction unit for extracting the first obstacle information from the wireless information; a second obstacle detection unit for detecting second obstacle information of a second obstacle which is at least one obstacle present in an own surrounding area by a sensor; and an overlap information removing unit which, if there is overlap obstacle information between the first obstacle information and the second obstacle information, removes the overlap obstacle information from the second obstacle information, to generate difference obstacle information.

Communication device and communication method

A semiconductor memory device of embodiments includes: a substrate; a memory pillar; first to sixth conductive layers provided above the substrate; first to sixth memory cells formed between the first to sixth conductive layers and the memory pillar, respectively; and a control circuit. The control circuit applies a first voltage to the first, second, a sixth conductive layer and applies a second voltage to the third, fifth conductive layer, then applies a third voltage to the first conductive layer, applies a fourth voltage to the sixth conductive layer, and applies a fifth voltage to the second conductive layer, and then applies a sixth voltage to the first conductive layer, applies a seventh voltage to the sixth conductive layer, and applies an eighth voltage lower than the fifth voltage to the second conductive layer.

Growing community of inventors

Yokohama, Japan

Takashi Maeda