Nec Electronics Corporation

Sony Semiconductor Solutions Corporation

Takashi Kusakari

Satoshi Yamamoto

Hiroaki Ono

Takato Shimoyama

Hiroyuki Takahashi

Hideo Inaba

Takuro Kamiya

Yukinao Kenjo

Hironaga Sano

Yasuhiro Okamoto

The present technology relates to a distance measuring device and a distance measuring method that enable distance measurement with an extended measurable distance range. The distance measuring device includes a control unit that controls a light emitting unit that emits irradiation light and a light receiving unit that receives reflected light of the irradiation light reflected by an object. In a first mode, control is performed on first imaging. In a second mode, control is performed on the first imaging, the second imaging, and third imaging. The distance is calculated from a first signal obtained by the first imaging and a second signal obtained by the second imaging, or the distance is calculated from the first signal, the second signal, and a third signal obtained by the third imaging.

Distance measuring device and distance measuring method

A distance measuring device of the present disclosure includes: a light source that irradiates a subject with light; a light detection unit that receives reflected light from the subject based on irradiation light from the light source; and a control unit that performs exposure control according to a distance between the distance measuring device and the subject. Furthermore, an electronic device of the present disclosure includes the distance measuring device having the configuration described above.

Distance measuring device, method for controlling distance measuring device, and electronic device

There is provided a method of entry of an operation mode of a semiconductor memory during operations without need of any specific timing specification and with effective suppression to any erroneous entry. If read cycles for plural addresses are continued, then a request for entry of operation mode is accepted (steps Sand S). In write cycles following to those read cycles, an operation mode to be entered is decided based on data externally designated, wherein in the first write cycle, the kind of the operation mode is set, and then in the next write cycle, conditions for the operation mode are set for the entry of the operation mode of the semiconductor memory.

Semiconductor memory device and method of entry of operation modes thereof

There is provided a method of entry of an operation mode of a semiconductor memory during operations without need of any specific timing specification and with effective suppression to any erroneous entry. If read cycles for plural addresses are continued, then, a request for entry of operation mode is accepted. In write cycles following to those read cycles, an operation mode to be entered is decided based on data externally designated, wherein in the first write cycle, the kind of the operation mode is set, and then in the next write cycle, conditions for the operation mode are set for the entry of the operation mode of the semiconductor memory.

Semiconductor memory and method for entering its operation mode

Problems are prevented that a refresh provides an influence to a normal access and that a continuation of write operations inhibits refresh. In a semiconductor memory device, a clock signal providing a reference to a time interval of refresh operations based on addresses corresponding to a single row s generated as a refresh clock signal. A transition of an access address &ldquo;Address&rdquo; externally supplied and corresponding to a memory cell is detected, so that a refresh operation is executed to a memory cell corresponding to a refresh address by triggering the generation of this detection signal before an access to a memory cell designated by the access address is made, wherein the upon input of a write enable signal /WE, the refresh is executed by triggering this signal before a write operation is executed and the refresh operation by triggering the generation of the access address is discontinued in a predetermined period of time based on the refresh clock signal.

Semiconductor memory device and refresh control circuit

A semiconductor storage having the same memory cells as a DRAM, operating in SRAM specifications, and having advantages such as a small chop size, a low power consumption, a low manufacturing cost, no access delay due to skew, and no memory cell breakdown. An ATD circuit ( ) generates a one-shot pulse added to an address change detection signal (ATD) from a change of the address (Address) supplied from external. By combining one-shot pulse produced for each bit of the address, only one one-shot pulse is generated even if the address includes skew. A memory cell is refreshed by using a refresh address (R_ADD) generated by a refresh control circuit ( ) during the time when a one-shot pulse is generated. At the fall of the one-shot pulse, a latch control signal (LC) is generated, and the address is taken in a latch ( ) so as to access a memory cell array ( ).

Growing community of inventors

Kanagawa, Japan

Takashi Kusakari