Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Takashi Kurusu

Takashi Izumida

Nobutoshi Aoki

Masaki Kondo

Kazuhiro Matsuo

Tsukasa Nakai

Tatsuya Kato

Shinji Mori

Makoto Fujiwara

Kenichiro Toratani

Masao Shingu

Masaaki Higuchi

Takahisa Kanemura

Hiroki Tokuhira

Hiroyoshi Tanimoto

Yuta Saito

Hikari Tajima

Hiroyuki Yamashita

Natsuki Fukuda

Tadayoshi Uechi

Kota Takahashi

Tomoki Ishimaru

Yuta Kamiya

Ha Hoang

Takeshi Murata

Ryota Narasaki

Takafumi Ochiai

Junichi Kaneyama

Muneyuki Tsuda

Shoji Honda

A semiconductor storage device includes a first conductive layer that extends in a first direction; a second conductive layer that extends in the first direction and is arranged with the first conductive layer in a second direction; a first insulating layer that is provided between the first conductive layer and the second conductive layer; a semiconductor layer that extends in the second direction and faces the first conductive layer, the second conductive layer, and the first insulating layer in a third direction; a first charge storage layer that is provided between the first conductive layer and the semiconductor layer; a second charge storage layer that is provided between the second conductive layer and the semiconductor layer; a first high dielectric constant layer that is provided between the first conductive layer and the first charge storage layer; and a second high dielectric constant layer provided between the second conductive layer and the second charge storage layer. At least a portion of the first charge storage layer faces the second charge storage layer without the second high dielectric constant layer being interposed between the portion of the first charge storage layer and the second charge storage layer in the second direction.

Semiconductor storage device

A semiconductor memory device includes a substrate, a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate, and a pillar extending through the multi-layered structure. The pillar includes a semiconductor body extending along the pillar, and a charge-storing film around the semiconductor body, the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers.

Semiconductor memory device with charge-diffusion-less transistors

An integrated circuit device according to an embodiment includes a semiconductor substrate, a first semiconductor member and a second semiconductor member provided on the semiconductor substrate, a first electrode disposed between the first semiconductor member and the second semiconductor member, and a second electrode disposed between the semiconductor substrate and the first electrode. The first semiconductor member and the second semiconductor member extend in a first direction perpendicular to an upper surface of the semiconductor substrate. The first semiconductor member and the second semiconductor member are separated in a second direction orthogonal to the first direction. The first electrode extends in a third direction intersecting both the first direction and the second direction. The second electrode extends in the third direction.

Integrated circuit device

In one embodiment, a semiconductor device includes a substrate, and a plurality of interconnects provided in the same interconnect layer above the substrate. The device further includes a plurality of insulators provided so as to be buried between the plurality of interconnects. Moreover, the plurality of interconnects include an interconnect group in which 2or more interconnects are successively arrayed so that correlation coefficients of line edge roughness (LER) between both side surfaces of the respective interconnects are positive, where N is an integer of 4 or more.

Semiconductor device and method of manufacturing the same

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Yokkaichi Mie, Japan

Takashi Kurusu