Renesas Electronics Corporation

Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kaisha

Takashi Kurafuji

Masamichi Fujito

Takahiro Yokoyama

Makoto Mizuno

Takashi Iwase

Yasunobu Aoki

Yuji Uji

Tomohiro Uchiyama

Shuichi Sato

Kenji Kawada

Akira Yamada

Yasuhiko Taito

Yoshihiko Asai

Satoshi Yamamoto

Tomoya Ogawa

Yoko Kimura

A master issues the valid data is specified when the data update processing is interrupted. The control unitstores in the storage unitthe second update status flag_, which indicates the update status of the first update status flag_and the second data_, which indicate the update status of the first data_, and the third update status flag_, which indicates the update status of the valid indication flag. When the determination based on the valid instruction flagis impossible, the usage data determination unitdetermines which of the first data_and the second data_is valid based on the values of the first update status flag_, the second update status flag_, and the third update status flag_

Information processing device and control method determining valid data in multiple memory areas based on multiple valid flags

To provide an information processing apparatus, a reading control method, and a computer readable storage medium that can improve the secrecy of information written in a secret area compared with the case of controlling access only by authentication, the information processing apparatus includes a nonvolatile memory that has a secret area where secret information is stored, an authentication controller that authenticates access to the nonvolatile memory, a flag information storage unit that stores flag information, and a memory controller that controls access to the nonvolatile memory by using the flag information stored in the flag information storage unit. The memory controller allows reading of the secret information from the secret area when a value of the flag information is a specified value and validity of access is authenticated by the authentication controller.

Information processing apparatus, reading control method, and computer readable storage medium

According to one embodiment, a memory controller is configured so that when the memory controller controls a writing/erasing process for a flash memory performed by a first or second master, the memory controller can prohibit, while the first master is performing the writing/erasing process for the flash memory, an interruption of the writing/erasing process in execution, the interruption resulting from access to the flash memory by the second master.

Semiconductor device and flash-memory control method

A storage device includes a data memory unit and a status memory unit. The data memory unit includes a pair of flash memory cells to be read by a complementary read mode, and 1-bit data is stored therein by the pair of flash memory cells. The status memory unit includes a flash memory cell to be read by a reference read mode, and a status flag is stored therein by the flash memory cell.

Storage device and storage method

An object of the present disclosure is to provide a semiconductor having high security. A semiconductor device includes: a memory region having a plurality of memory cells capable of storing data; a read circuit capable of switching a reference current reading method of reading data by comparing current flowing a memory cell to be read in the memory region with a reference current, and a complementary reading method of reading data by comparing currents flowing in first and second memory cells in which complementary data to be read in the memory region is stored; a register setting a security state; a mode controller setting a mode; and a control circuit controlling the reference current reading method and the complementary reading method of reading the data in the read circuit on the basis of a signal of setting a mode from the mode controller and a value of the register.

Semiconductor device

The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.

An access destination determining section determines whether an access is directed to regionor region. A regiondrive capability register and a regiondrive capability register set drive capabilities of output buffers when accesses to regionand regiongenerate, respectively. For example, if '1' is set to regiondrive capability register, when an access to regiongenerates, a Bufoutput enable signal is output at high level to enable outputs of Bufs. Therefore, a drive capability of a bus can be altered according to a region to which an access is made by a CPU or the like, thereby enabling prevention of unnecessary power consumption and generation of noise.

Bus control device altering drive capability according to condition

A microprocessor includes: a memory storing a program and various data; a processor core executing the program stored in the memory; an external bus interface serving as an interface portion of an external bus connected to an external device; a test circuit receiving a program counter value of an instruction to be executed by the processor core for outputting a test event signal for testing the microprocessor in synchronization with an operation timing of the processor core; a test event signal output terminal for outputting the test event signal to an external portion of the microprocessor, and an external event request signal input terminal provided for applying the processor core an external event request signal used by the external device to notify an event request with respect to the processor core.

Microprocessor internally provided with test circuit

A microprocessor includes a first bus and a second bus capable of operating simultaneously, a single port memory divided into a plurality of banks, a bus switch circuit provided between the plurality of banks and the first and second buses, and a processor core connected to the first and second buses and the single port memory. The bus switch circuit may be controlled statically, independent of activities on the buses, or may be controlled dynamically according to the activities.

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Tokyo, Japan

Takashi Kurafuji