Intel Corporation

Takashi Kumamoto

Kinya Ichikawa

Jiro Kubota

Masayuki Akiba

Eric Jin Li

Joshua Heppner

Mitul Bharat Modi

Xavier Francois Brun

Rajendra C Dias

Sufi Ahmed

Yoshishiro Tomita

Electromagnetically shielded electronic device technology is disclosed. In an example, a method of making an electronic device package can comprise providing a substrate having a conductor pad and an electronic component. The method can also comprise forming a conformal insulating layer on the substrate and electronic component. The conformal insulating layer conforms to the electronic component. The method can further comprise exposing the conductor pad. In addition, the method can comprise forming an electrically conductive electromagnetic interference (EMI) layer on the insulating layer and in contact with the conductor pad.

Electromagnetically shielded electronic devices and related systems and methods

A tape capable of laser ablation may be used in the formation of microelectronic interconnects, wherein the tape may be attached to bond pads on a microelectronic device and vias may be formed by laser ablation through the tape to expose at least a portion of corresponding bond pads. The microelectronic interconnects may be formed on the bond pads within the vias, such as by solder paste printing and solder reflow. The laser ablation tape can be removed after the formation of the microelectronic interconnects.

Laser ablation tape for solder interconnect formation

This invention relates to an apparatus and methods for increasing the microelectronic package density by stacking multiple microelectronic packages in an array and controlling package to package scalability without stressing the carrier substrates and without limiting the number of signal and input/output leads. Specifically, an intermediate substrate having conductive risers therein is used to enable pitch control of the package to package interconnection, control of the standoff distance and act as a microelectronic package stiffener.

Scalable microelectronic package using conductive risers

This invention relates to an apparatus and method for increasing microelectronic package density by stacking multiple microelectronic packages in an array and controlling package to package scalability without stressing the carrier substrates and without limiting the number of signal and input/output leads. Specifically, an intermediate substrate having conductive risers therein is used to enable pitch control of the package to package interconnection, control of the standoff distance and act as a microelectronic package stiffener.

Microelectronic package array

Systems and methods for encapsulating a stack of semiconductor dice are described. A stack of semiconductor dice may be formed, for example by attaching die to flexible printed circuit supports attached to frames and stacking the supports, and then encapsulated by flowing a liquid encapsulant around the stack of dice and solidifying the liquid encapsulant. The die supports may contain encapsulant flow openings, such as rectangular slits, that allow the liquid encapsulant to flow around the stack of dice.

Encapsulated stack of dice and support therefor

Encapsulation of a stack of semiconductor dice

Multi-purpose planarizing/back-grind/pre-under-fill arrangements for bumped wafers and dies, in which a planarizing coating provides improved and continued surface protection to the circuit surface of a wafer or die throughout back-grinding and subsequent mounting operations, and provides improved stiffening/strengthening of the wafer and die throughout back-grinding and subsequent mounting operations.

Pre-back-grind and underfill layer for bumped wafers and dies

A method for producing a molded flip chip package is described. According to one embodiment, an incomplete flip chip package comprising a thin substrate and a silicon chip is placed in a mold, and a resin is injected into the mold filling the gap between the surface of the flip chip and the adjacent substrate, and the resin is cured by maintaining the mold at an elevated temperature for a predetermined amount of time.

Molded flip chip package

Multi-purpose planarizing/back-grind/pre-underfill arrangements for bumped wafers and dies

A method for producing a molded flip chip package is described. The incomplete flip chip package comprising a thin substrate and a silicon chip is placed in a mold. A resin, preferably epoxy, is injected into the mold filling the gap between the surface of the flip chip and the adjacent substrate. Additionally, a stiffening structure is formed to increase the overall rigidity of the thin substrate specifically and the package as a whole.

Growing community of inventors

Ibaraki-ken, Japan

Takashi Kumamoto