Hitachi, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Takashi Koba

Keiichi Higeta

Masahiko Nishiyama

Naoyuki Anan

Seryung Park

Mikiko Sakai

A circuit system is provided capable of improving the throughput thereof by eliminating the operational constraint that if the operating frequency of a content addressable memory is lower than the operating frequency of a system LSI, two system clocks should be provided, or the higher frequency should be synchronized with the slower system clock. A clock control circuit () for down-converting an internal clock (&#x3a6;) of a LSI () is provided, and a control signal whose frequency is made lower is used to operate a content addressable memory circuit ().

Semiconductor integrated circuit and image processing system using the same

There is provided a control circuit () for fetching a result of a comparison of a part of bits of entry data with a corresponding bit of comparison data and prohibiting a comparison of residual bits in the entry data with the corresponding bit of the comparison data when the result of the comparison is mismatched, and the comparison of the residual bits in the entry data with the corresponding bit of the comparison data is prohibited. Consequently, the number of signal lines to be activated in one cycle of a comparing operation is decreased. Thus, a reduction in a consumed power can be achieved.

Semiconductor memory device

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Kodaira, Japan

Takashi Koba