Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Keiyo Engineering Co., Ltd.

Other

Hitachi Ulsi Engineering Corp.

Tdk Corporation

Mitsubishi Paper Mills Limited

Hitachi Engineering Co., Ltd.

Hitachi Ulsi

Takashi Kikuchi

Takao Okubo

Kunihiro Katayama

Kunio Uchiyama

Takashi Totsuka

Takashi Tsunehiro

Takeshi Suzuki

Takeshi Wada

Kenichi Kaki

Jun Kitahara

Hirokazu Aoki

Hajime Yamagami

Tsunehiro Tobita

Ryuichi Hattori

Yukihiro Seki

Masamichi Kishi

Shigeru Kadowaki

Hiroshi Fukuta

Manabu Saito

Yosio Takaya

Yasuhiko Saigou

Kanji Oishi

Susumu Hatano

Osamu Nishii

Katsuyuki Sato

Tadahiko Nishimukai

Takashi Wada

Nobuo Saito

Koji Igarashi

Hirokazu Ohkura

Hideaki Senoo

Takehiko Kumagai

Susumo Ogawa

Oichi Atoda

Yasuyuki Fuse

A semiconductor file system features a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating correspondence between physical and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information. The controller determines a physical sector address. The control section is for controlling input/output of data from/to the external system and for temporarily storing write data into the first nonvolatile memory from the external system in the volatile memory and then transferring the write data from the volatile memory to the first nonvolatile memory.

Flash memory control method and apparatus processing system therewith

A control method and system when a flash memory is used. as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller comprises control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address. The control section is responsive to the interface information, the first management information, and the second management information for controlling input/output of data from/to the external system and for temporarily storing write data into the first nonvolatile memory from the external system in the volatile memory and then transferring the write data from the volatile memory to the first nonvolatile memory. The consecutive address generation means and the sector address storage means output the physical sector address and the consecutively generated addresses to the first nonvolatile memory and the volatile memory when data at the physical sector address is output from the first nonvolatile memory or when data at the physical sector address is input to the volatile memory.

A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller has a control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address.

Flash memory control method and information processing system therewith

A tack sheet for ink jet recording, which comprises an ink jet recording sheet having at least one ink-receiving layer formed on one side of a support and an adhesive layer formed on the other side of the support, and a release sheet integrated thereto to cover the adhesive layer, wherein a cationic polymer is contained or impregnated in at least one of the support and the ink-receiving layer, and the ink jet recording sheet has an internal bond strength of from 120 to 320 g.multidot.cm/cm.sup.2 as measured in a wet state after being immersed in water at 20.degree. C. for 10 seconds, in accordance with TAPPI USEFUL METHODS NO. 403.

Tack sheet for ink jet recording

A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller comprises control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address.

Information processing system

Compressor/expander circuits which are built in a common semiconductor substrate along with a random access memory unit function so as to realize compression/expansion processes merely through the internal data transfer controls between the circuits and the random access memory unit as based on built-in control unit. This endows the temporary storage of data and the compression/expansion processes hereof with continuities, and achieves higher speeds for the compression/expansion processes.

Single semiconductor substrate RAM device utilizing data

The case has an opening and a wall section with a hole provided on the wall section and the wall section forms an inner space. The case also has a recessed area surrounding the hole. The piezoelectric diaphragm is supported around its periphery on top of the case so that an enclosure, including the hole, is formed within the inner space. An acoustic resistance sheet is bonded on to the wall section with the adhesive that is filled into the recessed area to close off the hole. With this structure, defective damping caused by seeping of the adhesive is prevented.

Piezoelectric transducer

A non-shared system with respect to an outside and an inside cache in a multi-processor system has multi-layer hierarchical cache. An invalidation address on a main memory address bus 31 in company with the rewriting of a main memory 30 is transmitted via a first and a second path 35, 36 to inside caches 11,21 so as to invalidate these inside caches 11, 21. The invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and outside caches 12, 22 so as to invalidate these outside caches 12, 22. It is extremely improbable for the address of access for writing to the transmitted to the main memory address bus 31 because the outside caches 12, 22 are operated in either copy back or write once system. As a result, even though the invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and the outside caches 12, 22, it is extremely improbably for the address of access for writing to conflict with a signal on the bidirectional connection.

Multi-processor system for invalidating hierarchical cache

A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and on output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

Static memory containing sense amp and sense amp switching circuit

In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.

Single-chip-cache-buffer for selectively writing write-back and

A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and an output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

Static memory containing sense AMP and sense AMP switching circuit

Single chip cache with partial-write circuit for transferring a

A main memory is subdivided into a shared region to undergo a write access from a plurality of processors and an input/output device and a plurality of private regions to undergo a write access only from the associated processor. Each of the cache devices includes a region discriminating circuit for determining whether an address generated from the processor is to be employed for an access to the shared region or to the private regions. If the access is to be conducted to the shared region, the cache devices operate according to the write-through method. On the other hand, if the access is to be conducted to the private region, the cache devices operate according to the copy-back method. When the processor or the input/output device rewrites data in the shared region of the main memory, the stored data of the shared region in the cache device of the processor is invalidated.

Multi-processing system and cache apparatus for use in the same

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Akishima, Japan

Takashi Kikuchi