Renesas Technology Corp.

Renesas Electronics Corporation

Hitachi-kokusai Electric Inc.

Hitachi, Ltd.

Hitachi Metals, Ltd.

Takashi Kawamoto

Masaru Kokubo

Manabu Nakamura

Taizo Yamawaki

Takashi Oshima

Yusuke Wachi

Tomoaki Takahashi

Yuta Sugiyama

Naoki Hongo

Yoichi Okubo

Hideyuki Nagaishi

Yasuhiro Takeda

Taizo Ito

Tomohiko Yano

Akira Maeki

Junya Dosaka

Shinya Kikuchi

Yoshimi Ishida

Hiromitsu Nishio

Takayuki Noto

A leakage voltage detection system can be easily mounted on a ground structure such as an existing street light or a traffic light and can detect a leakage voltage of an electric structure in real time. The leakage voltage detection system includes a sensor node mounted on a ground structure, and an equipment management server that determines a risk of a leakage voltage in the ground structure based on detection voltage information from the sensor node. The sensor node includes an electric field probe that measures a potential difference caused by an electric field detected by electrodes, and a sensor box that detects the potential difference between the electrodes of the electric field probe and transmits the potential difference to the equipment management server as a detection voltage. The equipment management server determines the risk of the leakage voltage where the sensor node is mounted based on the received detection voltage from the sensor node, and outputs information on determination of the risk of the leakage voltage.

Leakage voltage detection system and leakage voltage detection method

A resonator is supplied with voltage from a constant-voltage source, and the constant-voltage source outputs output voltage adjusted by a voltage adjustment signal to the resonator. The resonator outputs a clock signal having a frequency varied by varying capacitance in accordance with a received control signal and a frequency adjustment signal, and a frequency of the clock signal is varied by voltage output from the constant-voltage source.

Resonator, phase-locked loop, and semiconductor integrated circuit device

In a high frequency antenna switch module, an I/O interface generates various control signals for controlling a switch module on the basis of a system data signal and a system clock, a decoder generates a switch control signal SWCNT for controlling a switch in response to a control signal CNT in the control signals, a timing detector for switch-ports switching generates a switch-port switching detection signal t_sw in response to the switch control signal, a frequency control signal generator generates frequency control signals ICONT and CCONT in response to the signal t_sw, and a negative voltage generation circuit generates a negative voltage output signal NVG_OUT while switching the frequency of the clock signal generated in the negative voltage generation circuit to different frequencies in response to signals ICONT and CCONT. The switch switches the paths among the plural switch ports in response to the signals SWCNT and NVG_OUT.

High frequency antenna switch module

A clock data recovery circuit which has a high degree of jitter tolerance and can alleviate increase in the phase number of a multi-phase clock, power consumption, and a semiconductor chip area is provided. Each circuit of plural edge detection circuits comprises a first edge detection circuit and a second edge detection circuit. The first detection circuit detects that a data edge leads in phase more than &#x2212;1 phase from an edge detection phase, the second detection circuit detects that the data edge laggs in phase more than +1 phase from the edge detection phase. In response to the first output signal or the second output signal, the edge detection phase is changed by the amount of &#x2212;1 phase or +1 phase. When the data edge is detected in the range of &#xb1;1 phase, a next edge detection phase is maintained in the current state.

Clock data recovery circuit and transceiver semiconductor integrated circuit containing the same

The semiconductor integrated circuit incorporates a PLL circuit including a phase-frequency comparator, first and second charge pumpsand, a loop filter, a voltage-control oscillatorand a divider. The operation mode of the PLL circuit includes a standby state where locking is stopped, a lock response operation where locking is started and a steady lock operation where the locking started by the lock response operation is continued. In the steady lock operation, setting is made so that the second charge pumpis smaller in charge/discharge current than the first charge pump. The first and second charge pumpsandcharge and discharge the loop filterin response to outputs of the phase-frequency comparatorin reverse to each other in phase. In the lock response operation where locking is started, the second charge pumpis stopped from charging and discharging in reverse in phase.

Semiconductor integrated circuit

A phase locked loop (PLL) which has a desired frequency characteristic even though a manufacturing process of a semiconductor integrated circuit has fluctuations. The semiconductor integrated circuit includes the PLL and a control unit. The PLL has a phase frequency detector, a loop filter, a voltage controlled oscillator (VCO) and a divider. The VCO comprises a voltage-current converter (VIC) and a ring oscillator. In response to a control voltage, the VIC generates a control current for setting each operating current of the ring oscillator. The control unit switches the PLL to a calibration operating period of its open loop and a normal operating period of its closed loop.

Phase locked loop

A power circuit used for an amplifier, which includes an amplifier provided with a linear amplifier serving as a voltage source, a DC/DC converter serving as a current source, a hysteresis comparator controlling the DC/DC converter, and a current detector detecting output current from the linear amplifier to output the detected output current to the hysteresis comparator; and a switching restricting device for restricting a switching interval in the DC/DC converter such that the switching interval is not equal to or less than a constant time or is not shorter than the constant time.

Power circuit used for an amplifier

A DCDC converter includes a signal splitting unit that splits an input signal into N signal components; N DCDC converter elements that process individually the N split signals; and an adder that adds outputs from the plural DCDC converter elements to generate output signals. Each of the DCDC converter elements has an operation band narrower than an applicable frequency band of the input signal, and selects a design parameter that allows a conversion efficiency of the DCDC converter elements to be optimized for any band of the applicable frequency bands. For example, the parameter of a PMOS transistor and a NMOS transistor, which configure an inverter is designed to optimize the efficiency at any of frequency bands. The frequency band of the input signal is split, and each of the split outputs is input to a DCDC converter element that has a corresponding frequency and high efficiency characteristic.

DCDC converter unit, power amplifier, and base station using the same

Disclosed is a semiconductor IC device using a low-price oscillator, which is capable of bidirectional communication with a host and features a low price. In bidirectional communication between a host and a device, the device comprises a synchronization establishment unit, a frequency difference detector, a frequency generator, and an oscillator providing a reference signal. The synchronization establishment unit to which an output signal from the host is inputted outputs a received signal, a synchronization establishment signal and a reception data. The frequency difference detector detects a frequency difference between a received signal and a transmitting signal, and outputs a frequency coordination signal to the frequency generator. The number of frequency division of the frequency generator is controlled by the frequency coordination signal, and the frequency generator is capable of matching the frequency of the transmitting signal which is an output signal with the frequency of the received signal.

Transmitting/receiving device and communication system using the same

Disclosed are a high-efficiency power amplifier and base station device with respect to high-speed, broadband radio communication method. A broadband power supply circuit includes a linear voltage amplifier to which an input signal is applied, a resistor connected to an output side of the linear voltage amplifier, a switching regulator amplifying the voltage difference between both ends of the resistor to convert the amplified voltage difference into current, and a high frequency amplifier. The high frequency amplifier is designed to exhibit high efficiency at a frequency band where the efficiency of the switching regulator starts to be deteriorated, or at a high frequency band where the operation of the linear amplifier is dominant. In this case, the amplification of low frequency components are performed by the switching regulator, and the amplification of high frequency components are performed by the linear amplifier and the high frequency amplifier.

Power circuit and power amplifier and base station device using the same

To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, a charge pump, a loop filter, a frequency divider, a selector, and a voltage controlled oscillator. The frequency divider inputs an output signal and a reference signal, divides the output signal, and outputs a feedback signal, and also outputs a select signal, a trimming signal, and a limit signal from the output signal. The voltage controlled oscillator inputs the control voltage, the base voltage, the trimming signal, and the limit signal, changes the output signal frequency according to the control voltage so as to limit the upper limit frequency of the output signal. Also, the voltage controlled oscillator is capable of changing the frequency sensitivity of the output signal that is outputted with respect to the control voltage according to the trimming signal, and the upper limit frequency of the output signal according to the limit signal.

Phase Locked loop circuit and semiconductor integrated circuit device using the same

A technology capable of avoiding malfunction of a delay locked loop without generating a constant phase error in a delay locked loop circuit is provided. In a delay locked loop circuit, a control circuit is disposed in the outside of a delay locked loop, and in phase comparison of the delay locked loop, the control circuit outputs a control signal to the delay locked loop so that the relation in the phase comparison between a reference signal and an output signal is shifted by a set cycle.

Growing community of inventors

Kodaira, Japan

Takashi Kawamoto