Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Takashi Izumida

Nobutoshi Aoki

Masaki Kondo

Hikari Tajima

Tsukasa Nakai

Takahisa Kanemura

Tadayoshi Uechi

Nobuaki Yasutake

Hiroki Tokuhira

Toshiyuki Enda

Hiroyoshi Tanimoto

Takeshi Shimane

Kimitoshi Okano

Sanae Ito

Satoshi Inaba

Tatsufumi Hamada

Takashi Ichikawa

Takaya Yamanaka

Shinya Naito

Takayuki Kakegawa

Tetsuya Yamashita

Tomomi Kusaka

Takashi Kurusu

Takuyo Nakayama

Fumitaka Arai

Ichiro Mizushima

Atsushi Fukumoto

Takeshi Watanabe

Makoto Mizukami

Tatsuya Ohguro

Wataru Sakamoto

Tadashi Iguchi

Fumiki Aiso

Yoshiaki Shimooka

Kiyohito Nishihara

Hirokazu Ishida

Daigo Ichinose

Takayuki Okamura

Jyunichi Ozeki

Masakazu Goto

Noboru Ooike

Hiroki Okamoto

Yuki Sekino

Tomomi Yoda

Hirosyoshi Tanimoto

Michihito Kono

A semiconductor memory device, includes: a first region including a memory cell array; and a second region including a peripheral circuit. The second region includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes: a semiconductor region between the first and second surfaces; an n-type semiconductor region provided on the first surface and higher in donor concentration than the semiconductor region; a damaged region provided on the second surface; and a p-type semiconductor region provided between the damaged region and the n-type semiconductor region, closer to the second surface than the n-type semiconductor region in a direction from the first surface toward the second surfaces of the semiconductor substrate, and higher in acceptor concentration than the semiconductor region.

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a first stacked body in which a plurality of first conductive layers are stacked at intervals in a first direction above a semiconductor substrate; a second stacked body in which a plurality of second conductive layers are stacked at intervals in the first direction above the semiconductor substrate; and a first slit extending in a second direction perpendicular to the first direction, the first slit isolating the first stacked body and the second stacked body in a third direction perpendicular to the first and second directions.

A semiconductor device of an embodiment includes: a first and second semiconductor regions of a first conductivity type; a third semiconductor region of a second conductivity type disposed between the first and second semiconductor regions; a fourth semiconductor region of the first conductivity type disposed below the first semiconductor region; a fifth semiconductor region of the first conductivity type disposed below the second semiconductor region; a first region containing carbon disposed between the first and fourth semiconductor regions; a second region containing carbon disposed between the second and fifth semiconductor regions; a third region disposed between the first and second regions; the first and second regions having a first and second carbon concentrations respectively, the third region not containing carbon or having a lower carbon concentration than the first and second carbon concentrations in a portion below an end of a lower face of a gate electrode.

Semiconductor device

According to one embodiment, a semiconductor device includes an element region, an element isolation region adjacent to the element region, a gate insulating layer provided on an upper surface of the element region, and a gate electrode including a semiconductor layer, the semiconductor layer containing boron (B) and including a portion provided on the gate insulating layer, the element isolation region including an upper portion including an upper surface of the element isolation region and a lower portion including a lower surface of the element isolation region, and the upper portion of the element isolation region applying compressive stress to a portion of the element region, which is adjacent to the upper portion of the element isolation region.

A semiconductor device according to an embodiment includes a semiconductor layer having a first plane and a second plane opposite to the first plane; a gate electrode; a gate insulating layer provided between the first plane and the gate electrode; and a pair of first p-type impurity regions provided in the semiconductor layer on both sides of the gate electrode, containing boron, carbon, and germanium, having a bond structure of boron and carbon, having a first boron concentration and a first depth in a direction from the first plane toward the second plane, and having a distance between the first p-type impurity regions being a first distance.

Semiconductor device and semiconductor memory device

A semiconductor device includes a substrate, a semiconductor layer, a first interconnection, a second interconnection and a control electrode. The semiconductor layer includes a first channel portion and a second channel portion. The first channel portion and the second channel portion extend in a first direction crossing a front surface of the substrate. The first interconnection is connected to one end of the semiconductor layer, and extends in a second direction along the front surface of the substrate. The second interconnection is connected to the other end of the semiconductor layer. The control electrode extends along the front surface of the substrate, and extends in a third direction crossing the second direction. The control electrode includes a portion positioned between the first channel portion and the second channel portion. The control electrode is electrically insulated from the semiconductor layer.

According to one embodiment, a semiconductor device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a semiconductor body provided in the stacked body; and an insulating film. The semiconductor body includes a channel portion extending in a stacking direction of the stacked body, and a lower end portion of the semiconductor body provided between the channel portion and the substrate. The insulating film includes a charge storage film provided between the stacked body and the semiconductor body. A lower end portion of the insulating film surrounds the lower end portion of the semiconductor body. An upper surface of the lower end portion of the insulating film is provided at a lower height than an upper surface of the lower end portion of the semiconductor body in the stacking direction.

Method for manufacturing a semiconductor device including a vertical channel between stacked electrode layers and an insulating layer

Semiconductor device having vertical channel between stacked electrode layers and insulating layers

A semiconductor memory device according to an embodiment includes: a plurality of first conductive lines stacked in a first direction above a semiconductor substrate and extending in a second direction; a second conductive line extending in the first direction; semiconductor layers arranged between the first conductive lines and the second conductive line and extending in the first direction; a conductive layer in contact with a bottom surface of the semiconductor layer with a first impurity of a first conductivity type; and variable resistance films arranged at intersections between the first conductive lines and the semiconductor layer, the semiconductor layer having a first semiconductor part arranged from the bottom surface of the semiconductor layer to a position equal to or lower than a bottom surface of the first conductive line at a lowermost layer in the first direction with a second impurity of a second conductivity type.

A semiconductor memory device according to an embodiment includes a memory cell array that includes a plurality of memory cells. The memory cell array comprises: a plurality of first conductive layers that are stacked in a first direction above a substrate and extend in a second direction intersecting the first direction; a second conductive layer extending in the first direction; a variable resistance film provided at intersections of the plurality of first conductive layers and the second conductive layer; a first select transistor disposed closer to a side of the substrate than a lowermost layer of the plurality of first conductive layers, the first select transistor including a first select gate line intersecting the second conductive layer; a third conductive layer that extends in a third direction intersecting the second direction and is connected to a lower end of the second conductive layer via the first select transistor; and a second select transistor disposed between at least one pair of the plurality of first conductive layers adjacent in the first direction, the second select transistor including a second select gate line intersecting the second conductive layer.

According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of conducting layers, a semiconductor layer, a variable resistive element, and a first wiring. The plurality of conducting layers are laminated in a first direction at predetermined pitches. The conducting layers extend in a second direction. The second direction is along the surface of the substrate. The semiconductor layer extends in the first direction. The variable resistive element is disposed at an intersection point between the plurality of conducting layers and the semiconductor layer. The first wiring is opposed to an inside of the semiconductor layer via a gate insulating film. The first wiring extends in the first direction. The semiconductor layer at least includes a first part and a second part. The first part is upward of the conducting layer on a lowermost layer. The second part is downward of the first part. The first part has a first length in a third direction. The third direction is intersecting the first direction and the second direction, and is along the surface of the substrate. The second part has a second length in the third direction. The second length is shorter than the first length.

Nonvolatile semiconductor memory device

According to an embodiment, a semiconductor memory device comprises: a first semiconductor layer extending in a first direction; a first wiring line extending in a second direction intersecting the first direction; a variable resistance layer provided between these first wiring line and first semiconductor layer; and a first gate electrode extending in the first direction and facing the first semiconductor layer via a first insulating layer. In addition, this semiconductor memory device comprises a second gate electrode provided in the first direction with respect to the first wiring line, extending in the second direction in parallel to the first wiring line, and facing the first semiconductor layer. This second gate electrode faces the first semiconductor layer via a second insulating layer. Moreover, this second gate electrode faces the first gate electrode via the second insulating layer, the first semiconductor layer, and the first insulating layer.

According to an embodiment, a semiconductor memory device comprises: a first wiring line; a memory string connected to this first wiring line; and a plurality of second wiring lines connected to this memory string. In addition, this memory string comprises: a first semiconductor layer connected to the first wiring line; a plurality of second semiconductor layers connected to this first semiconductor layer; and a variable resistance element connected between this second semiconductor layer and the second wiring line. Moreover, of the first semiconductor layer and the plurality of second semiconductor layers, one includes a semiconductor of a first conductivity type, and the other includes a semiconductor of a second conductivity type.

According to an embodiment, a semiconductor device includes two electrodes extending in a first direction, a semiconductor layer provided between the two electrodes, an insulating film disposed between the two electrodes. The two electrodes are arranged in a second direction intersecting the first direction. The semiconductor layer extends in a third direction orthogonal to the first direction and the second direction. The insulating film covers a side surface of the semiconductor layer opposite to one of the two electrodes. The semiconductor layer has a shape in a cross section perpendicular to the third direction such that a width in the first direction at a center of the cross section is narrower than a width, in the first direction, of the side surface.

Growing community of inventors

Yokohama, Japan

Takashi Izumida