Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Kao Corporation

Sony Corporation

Sony Interactive Entertainment Inc.

Nohmi Bosai Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Takashi Itou

Yasuhiko Tsukikawa

Mikio Asakura

Yukiko Maruyama

Akio Ohba

Atsushi Kimura

Hiroyuki Segawa

Tetsugo Inada

Takashi Kohashi

Kyoji Yamasaki

Hirofumi Okamoto

Naohisa Kure

Kenichi Katou

Tomohiro Katou

Ken Onishi

Takashi Oda

Yoshinori Asamura

Yutaka Ikeda

Toru Yoshihara

Yoshiko Hatano

Tadashi Nomura

Yayoi Nakamura

Yuichi Yoshimura

Jiro Kawase

Manabu Tsukamoto

Kengo Aritomi

Tomoaki Sasaki

Koji Yui

Takashi Mizooku

Kei Miura

Takayoshi Kajino

Masato Oshika

Goro Hayakawa

Akira Yoshimatsu

Tetsuya Kawai

Eiichi Nishizawa

Shunsuke Endo

Katsuhiko Kimura

Michiko Asami

Aya Hirano

Miki Nakahira

Nakako Sato

Sachiko Tajima

Hiroki Ohtsuki

Masaki Shimoda

Yayoi Tsubouchi

Aya Miyaji

Mikako Matubara

Atsushi Uzu

Emiko Kouzu

Yoshiaki Itou

Mari Takeshige

Yuichiro Naoi

Hajime Yabu

An information processor includes: a similarity data generation portion generating similarity data that represents the calculated similarity to the image in the reference block in association with a position within the search range; a result evaluation portion detecting a position with a maximum similarity value for each piece of the similarity data and screening the detection result by making a given evaluation of the similarity; a depth image generation portion finding a parallax for each of the reference blocks using the detection result validated as a result of screening, calculating a position of a subject in a depth direction on a basis of the parallax, and generating a depth image by associating the position of the subject in the depth direction with an image plane; and an output information generation section performing given information processing on a basis of the subject position in a three-dimensional space using the depth image and outputting the result of information processing.

Information processor, information processing method, and computer program

An information processor includes: a similarity data generation portion generating, for a position within the search range, similarity data that represents the calculated similarity to the image in the reference block in association with the position within the search range; a similarity correction portion smoothing the similarity data in a direction of space on a basis of similarity data; a result evaluation portion detecting a position with a maximum similarity value in each piece of the smoothed similarity data; a depth image generation portion generating a depth image by associating the position of the subject in the depth direction with an image plane; and an output information generation section performing given information processing on a basis of the subject position in a three-dimensional space using the depth image and outputting the result of information processing.

There is provided an image processing device including an image input unit that performs image division on an input image, an evaluation value generation unit that generates an evaluation value based on an image signal of the input image, and a plurality of signal processing units that perform signal processing on the image signal based on the evaluation value generated by the evaluation value generation unit, wherein the plurality of signal processing units perform the signal processing using image signals of divided images divided by the image input unit.

Image processing device and image processing method

A combination smoke and heat detector which allows, in spite of a simple structure, light emitted from an indication lamp to be visually confirmed from a wide range of directions. The combination smoke and heat detector () includes a body base (), a printed circuit board (), a thermosensitive element (), a dark chamber (), an indication lamp () mounted to the printed circuit board (), a protective cover (), and a bar-like light guide () for guiding light emitted from the indication lamp () to the outside of the protective cover (). The light guide () passes through a light guide through-hole () formed in the protective cover () so as to be mounted therein, with one end surface thereof facing the indication lamp (), and another end surface thereof protruding to the outside of the protective cover () by a height substantially equal to or larger than a protruding height of the dark chamber (). Further, the light guide () is arranged opposite relative to the thermosensitive element (), with the dark chamber () being sandwiched therebetween.

Combination smoke and heat detector

Fire detector

A P-channel MOS transistor is provided between a terminal and an SVIH detection circuit for performing test mode detection. The P-channel MOS transistor is rendered non-conductive when a potential supplied to the terminal that is used commonly for signal input during the test setting and the normal operation is a power-supply potential EXTVDD or below. The SVIH detection circuit detects that a test mode is to be set when the potential at the terminal becomes higher than a prescribed potential. During the normal operation, the terminal is disconnected from the SVIH detection circuit so that the input capacitance of the terminal can be made to be about the same as that of another input terminal, and a high speed operation becomes possible. Moreover, there is no need to take into account the parasitic capacitance of an interconnection line leading to the SVIH detection circuit.

Semiconductor device with reduced terminal input capacitance

An input buffer circuit includes a first input buffer and a second input buffer. The first input buffer receives an external data signal and a reference potential to output an internal data signal. The second input buffer receives external data signals complementary to each other to output the internal data signal. The input buffer circuit causes either the first or second input buffer to operate in response to a control signal outputted from a control circuit. Due to this, this semiconductor memory device can correspond to various types of data processing systems.

Semiconductor memory device having select circuit

There is provided a semiconductor memory device including eight memory blocks to , first data bus , and second data bus . The eight memory blocks are arranged at respective eight of the total nine areas to defined in a three rows by three columns matrix except for a center area . A first data bus linearly extends between memory blocks in the first and second row of the matrix. A second data bus linearly extends between memory blocks in the second and third row of the matrix. The eight memory blocks includes a first group of the four memory blocks arranged adjacent the first data bus and connected to the first data bus and a second group of the four memory blocks arranged adjacent the second data bus and connected to the second data bus.

Semiconductor memory device with shortened connection length among memory block, data buffer and data bus

Hair dye compositions

Semipermanent hair dye composition

A semiconductor memory device is provided with a power supply circuit. The power supply circuit includes a reference voltage generating circuit which generates a first reference voltage, a booster circuit which generates a first internal power supply voltage by boosting an external power supply voltage using the first reference voltage, another reference voltage generating circuit which generates a second reference voltage, and a VDC circuit which generates a second internal power supply voltage by down-converting the first internal power supply voltage to a voltage level of the second reference voltage. The generated second internal power supply voltage is supplied to a DLL, and the DLL generates a periodic signal having a phase corresponding to the voltage level of the second internal power supply voltage.

Semiconductor memory device having a stable internal power supply voltage

In response to an output data width switching mode signal, a predecoder zone&plus;selector zone outputs selection signals SEL to SEL and WORDA to WORDC to a preamplifier&plus;write driver zone. The preamplifier&plus;write driver zone can switch connection between global I/O lines GIO< > to GIO< > and a data bus in response to these selection signals. Read data is output to a pad without through a selector circuit or the like on the data bus, whereby a simple structure can be obtained with no critical adjustment of a delay time resulting from mode switching or address change.

Semiconductor memory device capable of switching output data width

A row-related control circuit is provided which changes for a normal read operation and for refresh operation the delay time from a time at which a word line is activated to a time at which a sense amplifier is activated. Even when the refresh period is made longer and the charges in a memory cell are reduced, the sensitivity of the sense amplifier is heightened so that the refresh operation becomes possible. Thus, power consumption can be reduced by prolonging the refresh intervals.

Semiconductor memory device with reduced power consumption during refresh operation

A test on a desired internal voltage is easily and accurately conducted without increasing current dissipation or the number of pads. A driving circuit receiving a reference voltage from a reference voltage generating circuit has a high input impedance and low output impedance, and generates a voltage substantially at the same voltage level as the reference voltage received, and transmits the generated voltage to a pad with a current driving capability larger than the driving current capability of the reference voltage generating circuit.

Semiconductor integrated circuit device capable of externally monitoring internal voltage

Growing community of inventors

Hyogo, Japan

Takashi Itou