Nec Corporation

Renesas Electronics Corporation

Takashi Ishibashi

Hiroyuki Hashimoto

A semiconductor device includes a syndrome generation circuit configured to generate a syndrome code based on data and an error correction code corresponding to the data, an error determination circuit configured to detect a 1-bit error in the data based on the syndrome code, and multi-bit error detection circuit configured to determine whether the data detected to have 1-bit error includes a multi-bit error by using an error address of the data detected to have 1-bit error and an error syndrome code of the data detected to have 1-bit error.

Semiconductor device and error detection methods

A dynamic latch circuit which is fabricated in a semiconductor integrated circuit comprises a first circuit such as a clocked inverter and a second circuit such as an inverter. The first and second circuits are connected by a holding line. In the semiconductor integrated circuit, at least three interconnection layers are provided on a semiconductor substrate to be insulated by insulating layers, such that the holding line is provided as the secondly highest interconnection layer, and an output line of the second circuit is provided as the uppermost interconnection layer to be positioned on the straight upper side of the holding line. For this structure, a coupling capacitance which is formed between the holding line and a through line connected to a third circuit and provided as the uppermost interconnection layer is decreased.

Growing community of inventors

Tokyo, Japan

Takashi Ishibashi