Renesas Technology Corp.

Takashi Ippoushi

Tetsuya Watanabe

Toshiki Kanamoto

Masumi Yoshida

An FTI structure is employed in an isolation region making contact in a Y direction with a P-type impurity region serving as a drain region of a PMOS transistor. First, second and third N-type impurity layers serving as body regions are connected to a high potential line via fourth, fifth and sixth N-type impurity layers, respectively, and further via a seventh N-type impurity layer. The fourth to sixth N-type impurity layers are provided between an insulating layer of an SOI substrate and an element isolation insulating film in a PTI region.

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Tokyo, Japan

Takashi Ippoushi