Hitachi, Ltd.

Hitachi Chubu Software, Ltd.

Takashi Inagawa

Junya Ide

Yoshiaki Hisada

Hiroshi Takeda

Osamu Nishii

Shinji Kimura

Makoto Hanawa

Yasuo Hirata

Teiji Karasaki

Kazuhisa Ishida

Katuya Banno

A computer apparatus and a method of diagnosing are provided that increase reliability and make non-stop operation possible even at a hardware repair, replacement, or addition time. The computer apparatus, which comprises a main OS and a sub OS, may have a peripheral device or an I/O card repaired, replaced, or added with power on. The repaired, replaced, or added hardware component is disconnected from the main OS. With the main OS performing usual processing, the sub OS uses a test/maintenance program to check the operation of the repaired, replaced, or added hardware component and then passes the control of the hardware component to the main OS.

Computer apparatus and method of diagnosing the computer apparatus and replacing, repairing or adding hardware during non-stop operation of the computer apparatus

A bus switching structure and a computer using the same, wherein input/output (I/O) slot connections are switched to a desired I/O bus so that loads are distributed evenly over the I/O buses. The bus switching structure includes a switching unit and switching controller. The switching unit is located interposingly between an I/O slot and a plurality of I/O buses. The switching unit either connects or disconnects the I/O slot to or from each of the I/O buses in accordance with a switching signal. The switching controller outputs the switching signal to cause the switching unit to connect the I/O slot to one of the I/O buses and to disconnect the I/O slot from any of the other I/O bus, thereby effecting connection switchover between the I/O slot and the I/O buses.

Computer and a bus structure for switching the I/O slot connection

Bus switching structure and computer

Bus snoop method and apparatus for use in a computer system in which a CPU with cache is coupled to a main memory control unit for controlling a main memory unit through a bus snoop control unit, wherein when the CPU with cache occupies a bus at the time that an external bus master transfers data to the main memory unit, a transfer address for transfer of the data undergoes buffering in the bus snoop control unit and after the CPU with cache ends the execution of an instruction and opens a bus right, the bus snoop control unit transfers the data transfer address subject to buffering to the CPU with cache and a corresponding address recorded in the cache is canceled.

Bus snoop method and apparatus for computer system having CPU with cache

A processor for use in a data processing system with a cache RAM and main memory has a control pin for deactivating the driving of the data bus without deactivating that of the address bus during a write cycle. This capability is useful during a cache storing operation following a miss for performing a write operation without the requirement of additional address storing circuitry. In particular, during a cache storing operation, the processor can drive the address bus while control of the data bus by the processor is floated. Then, the data in main memory can be put on the data bus and transferred into the cache memory. Once the data is transferred to the cache memory, the original write operation can be completed.

Integrated circuit data processor including a control pin for

Growing community of inventors

Owariasahi, Japan

Takashi Inagawa