Oki Electric Industry Co., Ltd.

Lapis Semiconductor Co., Ltd.

Oki Semiconductor Co., Ltd.

Takashi Ichimori

Norio Hirashita

Toshiyuki Nakamura

A remote control device includes a light source for irradiating an instruction beam in a non-visible wave length range, and an operation unit for controlling the light source to irradiate the instruction beam when the operation unit is operated. An instruction beam detection apparatus includes an image capturing unit for capturing an image of the instruction beam irradiated from the light source of the remote control device within a detection range thereof; a storage unit for storing a first image captured with the image capturing unit; and a detection unit for detecting a position of the instruction beam on a second image according to a differential image between the first image stored in the storage unit and the second image newly captured with the image capturing unit.

Instruction beam detection apparatus and method of detecting instruction beam

Extracting information corresponding to a three-dimensional object from an image captured by plural imaging apparatuses is implemented with simple configuration and processing. Parallax information representing a parallax amount in the X direction of a pair of images captured by a pair of imaging apparatuses disposed at different horizontal positions is stored in a storage section, and a parallax correction control section reads out a parallax amount corresponding to a Y coordinate value of image data for one line input from a pre-image processing unit from the storage section and outputs a selection signal to selectors such that the output of one image data is delayed by the differential amount. A differential image generation unit calculates an absolute value of the differential of the pair of input image data for each pixel and outputs the result as a differential image for detecting the three-dimensional object.

Image processing apparatus, method, program, and recording medium

A semiconductor device includes diffusion layers formed in a SOI layer under a side-wall, a channel formed between the diffusion layers, silicide layers sandwiching the diffusion layers wherein interface junctions between the diffusion layers and the silicide layers are () silicon planes.

Semiconductor device having silicide layer completely occupied amorphous layer formed in the substrate and an interface junction of (111) silicon plane

A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of source and drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometric metallic silicides is X0 to Y0. X, Y, X0 and Y0 satisfy the following inequality: (X/Y)&#x3e;(X0/Y0).

Structure of a field effect transistor having metallic silicide and manufacturing method thereof

A memory cell structure comprises a first memory capacitor that is arranged in a first local area, and includes a first lower electrode, a first upper electrode, and a first dielectric oxide film interposed between the first lower electrode and the first upper electrode; a second memory capacitor that is spaced apart from the first memory capacitor and arranged in the first local area, and includes a second lower electrode, a second upper electrode, and a second dielectric oxide film interposed between the second lower electrode and the second upper electrode; and a first local interconnection layer.

Memory cell structure and semiconductor memory device

A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of a source and a drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometaric metallic silicides is Xto Y. X, Y, Xand Ysatisfy the following inequity: (X/Y)&#x3e;(X/Y).

A heat treatment for diffusing impurity ions implanted into a silicon layer is performed at a heat treatment temperature which is less than an aggregation temperature of the silicon layer. A thermal aggregation of the silicon layer can be inhibited, thereby reducing a silicon deficiency of the silicon layer.

Method of manufacturing a semiconductor device

A device isolation region made up of a silicon oxide film, which is perfectly isolated up to the direction of the thickness of an SOI silicon layer, and an activation region of the SOI silicon layer, whose only ends are locally thinned, are formed on an SOI substrate. A source diffusion layer and a drain diffusion layer of a MOS field effect transistor in the activation region are provided so that according to the silicidization of the SOI silicon layer subsequent to the formation of a high melting-point metal, a Schottky junction is formed only at each end of the activation region and a PN junction is formed at a portion other than each end thereof.

SOI MOS field effect transistor and manufacturing method therefor

A protective layer is formed on a metallic silicide layer prior to a heat treatment for reducing a resistance of the metallic silicide layer. As a result, vertical growing of crystallization in the metallic silicide layer is restrained by the protective layer during the heat treatment. Moreover, the crystallization in the metallic silicide layer easily grows along the protective layer. Therefore, evenness of the metallic silicide layer can be maintained.

Growing community of inventors

Tokyo, Japan

Takashi Ichimori