Kabushiki Kaisha Toshiba

Tokyo Electron Limited

Kioxia Corporation

Toshiba Memory Corporation

Takashi Ichikawa

Naoki Tamaoki

Akio Ui

Hiroshi Watanabe

Takashi Izumida

Kenichi Yamaga

Hisataka Hayashi

Toshiro Takase

Makoto Kobayashi

Tadayoshi Uechi

Tetsuya Yamashita

Takuyo Nakayama

Akihiro Kojima

Hideki Ito

Hideki Ogawa

Takanori Saito

Shinji Himori

Masaki Kondo

Nobutaka Kikuiri

Jun Abe

Hideichi Nakamoto

Hiroshi Akahori

Kiyohito Nishihara

Shigeo Kondo

Norikazu Yamada

Hidenobu Nagashima

Junko Hirokawa

Kazuaki Iwasawa

Takeshi Ohse

Kenji Kawabata

Takeshi Kaminatsui

Yingkang Zhang

Kazuhide Serizawa

According to one embodiment, a semiconductor memory device includes a first stacked body in which a plurality of first conductive layers are stacked at intervals in a first direction above a semiconductor substrate; a second stacked body in which a plurality of second conductive layers are stacked at intervals in the first direction above the semiconductor substrate; and a first slit extending in a second direction perpendicular to the first direction, the first slit isolating the first stacked body and the second stacked body in a third direction perpendicular to the first and second directions.

Semiconductor memory device

A topography simulation apparatus includes a processor and a memory connected to the processor. The memory stores instructions executable by the processor to set topographies of a material at N times Tto T(N is an integer of two or more) within a calculation region. The memory further stores instructions executable by the processor to develop the topographies of the material at the times Tto Tover time independently, calculate first to N-th values respectively representing a change in a topography of the material from the times Tto Tto times T' to T&#x2032;, and calculate a topography of the material at time T, based on the first to N-th values.

Topography simulation apparatus, topography simulation method, and topography simulation program

A substrate plasma processing apparatus includes a substrate holding electrode and a counter electrode which are arranged in a chamber, a high frequency generating device which applies a high frequency of 50 MHZ or higher to the substrate holding electrode, a DC negative pulse generating device which applies a DC negative pulse voltage in a manner of superimposing on the high frequency, and a controller controlling to cause intermittent application of the high frequency and cause intermittent application of the DC negative pulse voltage according to the timing of on or off of the high frequency.

Substrate plasma processing apparatus and plasma processing method

According to one embodiment, a nonvolatile memory device includes a substrate, first and second tunnel insulating films, first and second floating gate electrodes, an intergate insulating film and a control gate electrode. The substrate has first and second active regions isolated from each other by an element isolation trench. The first and second tunnel insulating films are located in the first and second active regions, respectively. The first and second floating gate electrodes are located on the first and second tunnel insulating films, respectively. The intergate insulating film includes a first insulating layer of a first insulating material, an electron trap layer of a second insulating material on the first insulating layer, and a second insulating layer of the first insulating material on the electron trap layer. The control gate electrode is located on the intergate insulating film.

Nonvolatile memory device

A calculating unit calculates either one of a reaction probability between a chemical species used in a semiconductor process and a semiconductor device and a deactivation probability of the chemical species, according to either one of a structure of the semiconductor device and a plurality of materials. A simulation unit performs a simulation of a physical phenomenon occurring in a reaction chamber based on either one of the reaction probability and the deactivation probability.

Simulating a chemical reaction phenomenon in a semiconductor process

A multi-dot flash memory includes active areas arranged in a first direction, which extend to a second direction crossed to the first direction, the first and second direction being parallel to a surface of a semiconductor substrate, floating gates arranged in the first direction, which are provided above the active areas, a word line provided above the floating gates, which extends to the first direction, and bit lines provided between the floating gates, which extend to the second direction. Each of the floating gates has two side surfaces in the first direction, shapes of the two side surfaces are different from each other, and shapes of the facing surfaces of the floating gates which are adjacent to each other in the first direction are symmetrical.

Multi-dot flash memory and method of manufacturing the same

A multi-dot flash memory set potentials of bit lines being disposed at a left side of a selected floating gate to V()&#x3e;V()&#x3e;V()&#x3e; . . . and set potentials of bit lines being disposed at a right side of the selected floating gate to V()&#x3c;V()&#x3c;V()&#x3c; . . . . Where V() is a plus potential and V() is a minus potential. The potentials of the bit lines converge on 0V with being away from the selected floating gate.

Multi-dot flash memory

A substrate plasma processing apparatus includes a chamber of which an interior is evacuated under a predetermined vacuum condition; an RF electrode which is disposed in the chamber and configured so as to hold a substrate to be processed on a main surface thereof; an opposing electrode which is disposed opposite to the RF electrode in the chamber; an RF voltage applying device for applying an RF voltage with a predetermined frequency to the RF electrode; and a pulsed voltage applying device for applying a pulsed voltage to the RF electrode so as to be superimposed with the RF voltage and which includes a controller for controlling a timing in application of the pulsed voltage and defining a pause period of the pulsed voltage.

Plasma processing apparatus of substrate and plasma processing method thereof

A simulation method includes dividing a material surface into finite computational elements, and calculating a deposition rate or etching rate at each of the computational elements to simulate a feature profile of the material surface, the calculating including calculating an indirect effect of a first computational element on the deposition rate or etching rate of a second computational element. The calculating the indirect effect includes correcting a surface profile at the first computational element on the basis of a surface structure around the first computational element, and calculating the indirect effect on the basis of the corrected surface profile at the first computational element.

Simulation method and simulation program

There is provided a heat processing furnace capable of quickly increasing and decreasing a temperature, while achieving improvement in durability. A heat processing furnacecomprises: a processing vesselfor accommodating an object to be processed w and performing thereto a heat process; and a cylindrical heaterdisposed to surround an outer circumference of the processing vessel, for heating the object to be processed w. The heaterincludes a cylindrical heat insulating member, and heating resistorsarranged along an inner circumferential surface of the heat insulating member. Each of the heating resistorsis formed of a strip-shaped member that is bent into a waveform having peak portions and trough portions. Pin membersare arranged in the heat insulating memberat suitable intervals therebetween, the pin membersholding the heating resistorsuch that the heating resistoris movable in a radial direction of the heater.

Heat processing furnace and vertical-type heat processing apparatus

The present invention is a heat processing furnace comprising: a processing vessel for accommodating an object to be processed and performing thereto a heat process; and a cylindrical heater disposed to surround a circumference of the processing vessel, for heating the object to be processed; wherein: the heater includes a cylindrical heat insulating member, ribbed shelf sections that are axially formed in a tier-like manner on an inner circumference of the heat insulating member, and heating resistance wires of a helical pattern that are placed along the respective shelf sections; and pin members are arranged in the heat insulating member at suitable intervals therebetween, the pin members holding the heating resistance wires such that the heating resistance wires are movable in a radial direction of the heater, while preventing dropout of the heating resistance wires from the shelf sections.

The present invention is a thermal processing method including: a step of conducting a predetermined thermal process in a low temperature zone to a plurality of objects to be processed held in a tier-like manner by a heating unit, in a processing container that is made of metal and has the heating unit therein, and a step of introducing a cooling gas into respective areas in the processing container divided in a height direction of the objects to be processed.

Thermal processing method and thermal processing unit

An outer body of ball shell type has an opening. A camera is located in the outer body and receives an image from outside of the outer body through the opening. A camera support unit is located in the outer body and rotationally supports the camera along a first axis and a second axis mutually crossed at a center of the outer body. A first camera actuator is located in the outer body and rotationally actuates the camera around the first axis. A second camera actuator is located in the outer body and rotationally actuates the camera around the second axis.

Growing community of inventors

Saitama, Japan

Takashi Ichikawa