Fujitsu Corporation

Takashi Ibi

Moriyuki Takamura

Shigeru Mukasa

A memory control device and method receives a request to transfer a series of first-unit K byte (for example, 512) data in an address space, divides the first-unit K into second-unit L (for example, 64), assigns priority levels to the second-unit L, issues plural times a data transfer instruction to transfer the L-byte data to a memory device comprising a plurality of memories operable in a consecutive access mode, and thus accesses memories in response to the request to transfer the K-byte data. The L-byte data are sequentially allocated in third units S (for example, 64) specified by the data transfer instruction to the memories. The third unit is equal to L or is obtained by dividing L, and is a multiple of an activation unit of the memories. The S-byte data are accessed in the allocated memories in the consecutive access mode.

Memory control device and method operated in consecutive access mode

Partial-store access in which a portion of data is changed, is performed using a plurality of memory banks in a memory unit. The partial store-access is performed through an interleave method in which read-data which is one word in length is read from the memory banks during an access time. The one word write-data including a portion of data which is to be changed, is registered in store-data registers. The portion of data is changed in an overwriting operation within the access time. When more than one portion of data is to be changed, such portion is also changed within the access time, but within a different register (i.e., at a later time) than the portion of the storing data initially changed. A positional signal indicating the position of the storing data which is to be changed, is stored in position-signal registers. The portions of the storing data which have been changed are combined using the positional signals, with the one word read-data read from the memory banks, thus producing rewrite-data after the access time. The rewrite-data is then restored in the memory banks.

Partially storing control circuit used in a memory unit

An apparatus for reading data from a memory in a computer system includes: an address register for holding an address to be supplied to the memory, a read data register for holding data read out from the memory and a device for generating a gated clock signal from a free-running clock signal having a predetermined constant period of time. The gated clock signal is free-running with the predetermined constant period of time in a normal clock mode but is generated by a single pulse with an interval longer than the period of the free-running clock signal in a single clock mode. A device, having serially connected plural registers for shifting a trigger signal in accordance with the free-running clock signal generates a read data clock signal. The trigger signal has a same timing synchronized with a specific phase of the gated clock signal at which a phase of the address register is switched to hold a new address to be supplied to the memory. The shifted trigger signal is fed to the read data register for hodling the data read out from the memory.

Dual mode memory read cycle time reduction system which generates read

An error correcting and detecting system using a parity check H-matrix divided into a plurality of block vectors each including four or three column vectors each having eight elements. In the H-matrix, (i) there are no all '0' vectors; (ii) all column vectors are different from each other; (iii) 8 column vectors each having only one '1' is included therein, (iv) each column vector has an odd number of '1's'; (v) the modulo-2 sum of any three column vectors within any block never equals any column vectors of the H-matrix; (vi) the modulo-2 sum of four column vectors within any block never equals an all '0' vector; and (vii) the modulo-2 sum of eight column vectors within any two blocks never equals an all '0' vector.

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Kawasaki, Japan

Takashi Ibi