Hitachi, Ltd.

Renesas Technology Corp.

Takashi Hotta

Shigeya Tanaka

Masahiro Iwamura

Hideo Maejima

Yasuhiro Nakatsuka

Kotaro Shimamura

Tadaaki Bandoh

Kazuo Kato

Fumio Murabayashi

Kozaburo Kurita

Hiromichi Yamada

Hideo Sawamoto

Sin-ichi Sinoda

Akiyoshi Osumi

Yoshitaka Takahashi

Tetsuya Shimomura

Koji Saito

Tatsumi Yamauchi

Toshihiko Kurihara

Masahiko Saito

Yuichiro Morita

Nobuyasu Kanekawa

Akira Bando

Shigeta Ueda

Koyo Katsura

Haruo Yoda

Mutsumi Kikuchi

Ikuro Masuda

Kenichi Kurosawa

Shoji Yoshida

Kazutaka Mori

Mitsuji Ikeda

Takashi Sase

Keisuke Nakashima

Takanaga Yamazaki

Yoshiki Kobayashi

Kazushige Yamagishi

Hidemitsu Naya

Yutaka Okada

Kazuhiro Imaie

Mitsuyasu Kido

Masahiro Ueno

Dai Fujii

Hidehito Takewa

Tatsuki Inuduka

Yoshikazu Kiyoshige

Takeshi Takemoto

Manabu Jyou

Syoji Yoshida

Takeshi Takehara

Kouzaburou Kurita

Shigeru Shibukawa

Noboru Akiyama

Teppei Hirotsu

Hirokazu Suzuki

Takashi Akioka

Hirokazu Aoki

Koji Sakamoto

Kazumi Hatayama

Noriyasu Ido

Michinobu Nakao

Hisao Sasaki

Kenji Jin

Takahiro Nishiyama

Katsuichi Tomobe

Yuuichiro Morita

Yoshiki Fujioka

Hiroyasu Satou

The basic section of the multimedia data-processing system includes a CPU, an image display unit, a unified memory, a system bus, and devices, andconnected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unitand display control unit. Main storage areaand display areaare stored within the unified memory. Unified memory portfor connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

Memory access methods in a unified memory system

The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A plurality of instructions read in the instruction registers in one machine cycle at a time are processed in parallel by the plurality of arithmetic operation units.

Data processor

A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Data processor having cache memory

In a synchronization system adopted in a synchronous-multisystem control apparatus comprising a plurality of systems operating synchronously with each other at a fixed control period, the synchronous-multisystem control apparatus can be operated in a single-system mode in the event of failures occurring simultaneously in some of the systems. The synchronous-multisystem control apparatus employs a plurality of control circuits each provided for one of the systems. Any particular one of the control circuits comprises:

Synchronization system and synchronization method of multisystem control apparatus

An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal Kwhich is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal Kand the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.

Information processor and information processing system utilizing interface for synchronizing clock signal

An apparatus for calculating a normalized correlation coefficient used as a similarity evaluation measure by using image data values of pixels in a template image and image data values of pixels in a subimage, included in a search image, corresponding to the template image, has a memory that stores image data values of pixels in the search image and calculating means that calculate a sum of image data values of pixels in the template image and a sum of image data values of pixels in the first rectangular region in the search image or a sum of squares of image data values of pixels in the template image and a sum of squares of image data values of pixels in the first rectangular region in the search image. Normalized correlation coefficient calculating means calculate a normalized correlation coefficient on the basis of the sum of image data values of pixels in the template image and the sum of image data values of pixels in the first rectangular region in the search image, or the sum of squares of image data values of pixels in the template image and the sum of squares of image data values of pixels in the first rectangular region in the search image.

Statistic calculating method using a template and corresponding sub-image to determine similarity based on sum of squares thresholding

A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein

Consumption power control is provided for a system LSI made of a combination of a plurality of reusable logic circuit modules, i.e., Intellectual Property (IP) cores. Hardware resources such as interfaces and registers for the consumption power control of other IP cores are prepared and controlled by software for the consumption power control of a system LSI. The consumption power can be controlled at an IP core level. A method is provided which facilitates a system LSI designer to enter a consumption power control specification of a system LSI when the system LSI is configured.

Logic circuit module having power consumption control interface and a recording medium storing the module

A phase locked loop (PLL) circuit is provided to operate in a broad band, including two separate loops one of which is for feed-back of an output from an oscillator to the same oscillator through its associative proportional control unit and the other of which is for feed-back of an output of an oscillator to the same oscillator via an integral control unit. The proportional control unit is arranged to control an output frequency of the oscillator and is operable to generate a control signal based on a difference between input and output signals. The integral control unit is arranged to control the phase of an output signal of the oscillator to thereby generate a control signal based on a phase difference between input and output signals.

Phase-locked loop circuit, information processing apparatus, and information processing system

An image processing apparatus obtains a sum A of image data values of pixels in a template image, a sum B of squares of image data values of pixels in a template image, a sum C of image data values of pixels in a sub-image to be processed, of a search image, a sum D of squares of image data values of pixels in the sub-image of the template image, further obtains a threshold value F in advance by using the obtained values A, B, C and D, the number P of pixels in the template image, and the preset value E. Moreover, the apparatus obtains a square of each difference between an image data value of each pixel in the sub-image and that of a corresponding pixel in the template image, and performs cumulative addition for each obtained squares. If the result of cumulative addition exceeds the above-mentioned threshold value, the apparatus closes processing evaluation of a similarity between the sub-image and the template image. Furthermore, the apparatus recursively obtains a moving-average value of image data values of pixels in a rectangular region to be presently processed, by using a moving-average value for a rectangular region which was previously processed and image data read from a first memory and a second memory, each memory stores image data by one line pixels of the image, which include image data of pertinent pixels in the rectangular regions.

The basic section of the multimedia data-processing system includes a CPUan image display unita unified memorya system busand devicesandconnected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unitand display control unitMain storage areaand display areaare stored within the unified memory. Unified memory portfor connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

In an information processing apparatus, a user having no knowledge of a designer of an LSI modifies a floorplan of the LSI without deteriorating the performance of the LSI. The designer who designs the LSI uses a circuit designing apparatus to store circuit information including a functions of each of blocks constituting the LSI, a floorplan regarding allocation of the blocks, and evaluation indices which are the know-how of the designer, with being associated with each other. The user uses a floorplan modifying apparatus to modify the floorplan and to evaluate the modified floorplan according to the evaluation indices.

Information processing apparatus, information processing system, and storage media

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Hitachi, Japan

Takashi Hotta