Fujitsu Corporation

Takashi Horii

Yoshihiro Takemae

Junji Ogawa

Masao Nakano

Tomio Nakano

Yasuhiro Fujii

Takeo Tatematsu

Norihisa Tsuge

Kimiaki Sato

Norihisa Tsuge, Deceased

Hiroshi Yamamoto

Makoto Yanagisawa

Nobumi Kodama

Kiyonori Ogura

Yasuhiro Takada

Takeo Takematsu

Sachie Tsuge

Itaru Tsuge

A semiconductor memory device has a first control signal is externally input to an input buffer circuit. A second control signal output from the input buffer circuit is input to an internal circuit. The internal circuit comprises a memory cell array having a number of memory cells and peripheral circuits for writing and reading cell information in and from the memory cells, and the writing and reading operations are executed based on the second control signal. Read data output from the internal circuit is input to an output buffer, which outputs the read data as output data. Power from a common power supply is supplied to the input buffer circuit and the output buffer. A noise-remove signal generator, which is connected to the input buffer circuit, functions based on either one of the first control signal and the second control signal to generate a noise remove signal in synchronism with an output timing of the output data. A noise removing circuit removes noise from the second control signal based on the noise remove signal.

Semiconductor memory device

A semiconductor memory device includes: a memory cell array constituted of a plurality of memory cell array units; transfer gates inserted in bit lines between the adjacent memory cell array units; a first and a second column decoders connected to both ends of bit lines in which the transfer gates are inserted; a row decoder connected to word lines of the memory cell array. The row decoder is adapted to be divided selectively in two parts; and two sets of row/column addresses are supplied to the column decoders and the row decoder. Therefore, simultaneous separate accesses to the memory cell array are carried out by the two sets of row/column addresses.

Simultaneous dual access semiconductor memory device

A one-transistor one-capacitor type semiconductor memory device having a detection circuit for detecting the electric potential of a word line, to determine an appropriate timing for driving a sense amplifier, thereby improving the speed of memory operations.

Semiconductor memory device with a detection circuit to detect word line

A semiconductor integrated circuit including a memory unit for storing address information of a failed circuit portion and for replacing the failed circuit portion by a redundant circuit portion. The semiconductor integrated circuit provides a comparison unit for detecting coincidence between data read from the memory unit and a received input address. Data produced from the comparison by the comparison unit is delivered through an external connection terminal.

Semiconductor integrated circuit with redundant circuit replacement

A device connected between first and second voltage feed lines includes an information storing circuit having a fuse for storing information by blowing or not blowing the fuse, a voltage level conversion circuit connected to at least one of the first and second voltage feed lines and outputting a voltage lower than a voltage between the first and second voltage feed lines to the information storing circuit, and a circuit connected between the first and second voltage feed lines, for outputting a detection signal in response to a voltage value at the fuse in the information storing circuit to which the voltage is applied from the voltage level conversion circuit and which voltage value is varied with the blown or unblown state of the fuse. In a normal operation, the voltage output from the voltage level conversion circuit can be set as low as possible to restrain electromigration caused at the vicinity of the blown portion of the fuse to which the voltage is applied, but higher than the threshold voltage of the information detection circuit.

Semiconductor integrated circuit device having fuse-type information

A circuit for storing information by blown and unblown fuses has at least two fuses per bit and an information output circuit. The information output circuit discriminates between the state in which all the fuses are unblown and the state in which at least one of the fuses is blown, and provides an output in accordance with the result of the discrimination as stored information.

Information storing circuit using blown and unblown fuses

A semiconductor integrated circuit which includes therein at least one inspection circuit for inspecting a voltage level produced at an internal node to be inspected. The inspection circuit has at least a control signal input portion connected to the internal node to be inspected and an input part connected to an external input/output pin. The inspection circuit includes a series-connected transistor and diode connected between a power source and the input portion, a capacitor connected between a gate of the transistor and the input portion, and a transfer gate transistor connected between the control signal input portion and the gate of the transistor. The inspection circuit discriminates the level at the internal node according to a flow or nonflow of a current, via the external input/output pin, when a particular signal having a voltage level higher than the power source level is supplied to the external input/output pin.

Semiconductor integrated circuit

An MIS transistor circuit which is operated alternately in a reset state and in an active state, comprises a voltage holding circuit for holding a power supply voltage applied in each reset state so as to provide a clamped voltage. The clamped voltage is applied during each active state to the desired nodes of the MIS transistor circuit as an actual power supply voltage, whereby error operation due to voltage fluctuation of the power supply voltage is prevented.

Growing community of inventors

Kawasaki, Japan

Takashi Horii