Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Roland Kabushiki Kaisha

Takashi Hirata

Hironori Akamatsu

Toru Iwata

Satoshi Takahashi

Yutaka Terada

Yoshihide Komatsu

Hiroyuki Yamauchi

Tadahiro Yoshida

Keiichi Kusumoto

Yukio Arima

Shiro Dosho

Shiro Sakiyama

Yusuke Tokunaga

Hirokazu Sugimoto

Junji Nakatsuka

Takefumi Yoshikawa

Tsuyoshi Ebuchi

Yasuyuki Doi

Koichi Sugimoto

Makoto Hattori

Hisanori Yuki

Hideki Yoshii

Satoshi Hori

The charge pump circuit includes: a first switch for controlling either one of push operation and pull operation based on a first control signal; a current mirror circuit composed of a transistor different in attribute from the first switch; and a second switch composed of a transistor same in characteristic as a transistor constituting the first switch, for controlling input of a current into the current mirror circuit based on a second control. The other operation, the push operation or the pull operation, is performed with a current output from the current mirror circuit.

Charge pump circuit

An AC-coupled interface circuit on a semiconductor integrated circuit apparatus performing a bidirectional data transfer via a differential transmission line includes a differential driver, a differential receiver and a potential setting section. The differential driver includes a pair of output terminals connected to a pair of signal lines. The differential receiver includes a pair of input terminals connected to the pair of signal lines. In a data transmission operation, the differential driver converts transmit data to a differential signal to output the differential signal. In a data reception operation, the differential receiver receives a differential signal transferred to the pair of signal lines and converts the differential signal to receive data. The potential setting section sets a potential of the pair of signal lines to a predetermined stable potential before the differential signal is transferred to the pair of signal lines.

AC-coupled interface circuit

A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.

Delay locked loop circuit

A resynchronization circuit possesses a sufficient migration margin even when the speed of a clock signal used for outputting data is increased, so that the data transfer speed can be increased. In the resynchronization circuit, a determination circuit holds a signal which is determined according to the phase difference between a determination signal and a reference clock signal (determination result). In a synchronization circuit block, a received data signal is held in synchronization with a strobe signal. Then, the received data signal is held in synchronization with a clock signal which has the same frequency as that of the reference clock signal and has a phase determined according to the determination result and output from the resynchronization circuit.

Resynchronization circuit

A charge pumping circuit includes a first switch for controlling one of push and pull operations in accordance with a first control signal; a current mirror circuit constructed from transistors each having a different polarity from the first switch; a second switch for controlling current input to the current mirror circuit in accordance with a second control signal, the second switch being constructed from a transistor having the same characteristic as a transistor used for constructing the first switch; a first MOS capacitor one end of which is connected to an input side of the current mirror circuit; a second MOS capacitor receiving, at one end thereof, a current concerned with the push and pull operations; and a voltage buffer connected to the first and second MOS capacitors. The other of the push and pull operations is performed with an output current of the current mirror circuit.

Charge pumping circuit

A first semiconductor integrated circuit is connected to a second semiconductor integrated circuit with a cable. In the first semiconductor integrated circuit, when a power supply voltage becomes less than a set voltage detection level, a voltage-detecting circuit outputs a voltage-detected signal to lower the voltage of the cable and to stop the operation. The second semiconductor integrated circuit detects the decrease in the voltage of the cable to recognize the halt of the operation of the first semiconductor integrated circuit. In the first semiconductor integrated circuit thus configured, in testing the operation under low-voltage conditions in which the power supply voltage is less than the set voltage detection level, the voltage-detecting circuit receives a control signal from an external terminal to stop the operation forcibly. Consequently, even when the power supply voltage is made lower than the set voltage-detecting level, the first semiconductor integrated circuit properly operates until the power supply voltage reaches a predetermined lower limit of operating voltage. Thus, evaluation of operation is possible under low-voltage conditions.

Semiconductor integrated circuit with voltage-detecting circuit and signal transmitting and receiving system

A synchronization circuit includes a state detection circuit for outputting a control signal according to the temporal relationship between a transition point of an input signal and an edge of a synchronization clock, a delay selection circuit for adding a delay to the input signal based on the control signal, and a latch circuit for synchronizing the signal outputted from the delay selection circuit with the synchronization clock. Therefore, synchronization of the input signal can be carried out without adding latency to the input signal.

Synchronization circuit

A network apparatus is provided, which allows another network apparatus to recognize the disconnection with reliability, if a power supply to the network apparatus is interrupted. A control unit operating with a first power supply outputs a first signal, which is level-converted and supplied as a second signal to an intermediate potential supply unit operating with a second power supply. In the intermediate potential supply unit, a switch receives a reset signal as a switch signal and outputs, when the power supply is interrupted, a ground potential to a driver instead of the second signal. As a result, an intermediate potential supplied to a cable is forcibly set to the ground potential.

Network apparatus

A multi-phase clock transmission circuit includes: a clock generator for generating a clock synchronizing with a reference clock and a control signal responsive to the phase difference between the reference clock and the generated clock; and a delay circuit for generating a multi-phase clock based on the clock and the control signal. The clock generator generates a signal having a frequency equal to an integral multiple of the frequency of the reference clock and outputs the signal as the clock. The delay circuit has a circuit receiving the clock and including a plurality of delay elements in cascade connection each giving a delay according to the control signal to an input signal. Signals output from the plurality of delay elements are used as signals constituting the multi-phase clock.

Multi-phase clock transmission circuit and method

First and second nodes are coupled together by a bus. The first node includes a detecting circuit for detecting the maximum data transfer capability of a connected node, at least two receiving circuits for receiving data from the bus, and a controlling circuit for selecting, based on an output signal from the detecting circuit and for optimizing the configuration of a receiving unit so as to bring the other of the receiving circuits to a stop. The second node includes a transmitting circuit for transmitting data to the bus and a notifying circuit for notifying the first node of its own maximum transfer capability.

Data transferring device

A power-saving network unit, which is connected to a network made up of a plurality of power-saving network units, includes: network monitoring means; network information memory; power-saving mode setting means; peripheral I/O interface; and digital processor. The network monitoring means monitors a topology of the network, or the interconnection relationship among the power-saving network units. Every time the network has been modified, the network monitoring means stores the modified network topology on the network information memory. The power-saving mode setting means receives the network information stored on the network information memory. If the power-saving network unit is a master or relay node in the network, then the power-saving mode setting means locks the peripheral I/O interface and digital processor of the power-saving network unit to the normal operation mode and prohibits these sections from entering the power-saving mode.

Network unit with power saving mode inhibit based on interconnection relationship to neighboring nodes which is stored on the unit

A voltage control circuit for implementing, e.g., the CPS function in which a high-accuracy comparison is performed between a high external voltage and a reference voltage. A diode-connected transistor converts the external voltage to a voltage lower than the external voltage in conjunction with an external voltage dropping resistor. A comparator compares the converted voltage with a specified comparison voltage. The size of the transistor is determined such that the ratio of an increment of the converted voltage to an increment of the external voltage is sufficiently high in a comparison region in which the external voltage is close to the reference voltage. A clamping circuit clamps the converted voltage with a specified limit voltage such that the converted voltage does not exceed the withstand voltage of the circuit.

Voltage control circuit network device and method of detecting voltage

In the circuit for detecting the voltage level of an analog signal, a conversion circuit converts an analog signal to digital signals by comparing the voltage level of the analog signal with a plurality of reference potentials. A filter circuit matches timings of at least either rising edges or falling edges of the digital signals with each other. This prevents malfunction in the voltage level detection.

Voltage level detection circuit and voltage level detection method

A semiconductor integrated circuit includes receiver, potential sensor and output fixing circuit. The receiver receives a differential signal that has been transmitted through a twisted pair of signal lines, and outputs a signal in accordance with the differential signal. The potential sensor senses a variation in in-phase potential of the differential signal transmitted through the twisted pair. And the output fixing circuit fixes an output of the receiver at a certain value if the variation sensed by the potential sensor is equal to or greater than a predetermined level. In this configuration, once the variation in the in-phase potential of the differential signal has reached the predetermined level, the output of the receiver is fixed at the certain value. Accordingly, even if the receiver operates erroneously due to the in-phase potential variation, the erroneous output of the receiver is not supplied to the next stage like a digital section.

Semiconductor integrated circuit realizing electrical interface

An LSI core includes a first terminal; a second terminal; and a voltage generation circuit for generating a voltage. The first terminal is connected to a first external line provided outside the LSI core. The second terminal is connected to the first external line and to a second external line provided outside the LSI core. The voltage generation circuit includes a voltage generation section for generating the voltage, an output section for outputting the voltage generated by the voltage generation section to the first external line through the first terminal, and an input section for receiving the voltage, output to the first external line by the output section, through the second external line and the second terminal.

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Osaka, Japan

Takashi Hirata