Agilent Technologies, Inc.

Jds Uniphase Corporation

Viavi Solutions Inc.

Avago Technologies Fiber IP (singapore) Pte. Ltd

Other

Avago Technologies Fiber IP Pte Ltd.

Takashi Hidai

Frederick W Miller

Michael Allen Robinson

Peter Henry Mahowald

Slawomir K Ilnicki

Canning Hsueh

Martin Curran-Gray

Sam Bauer

Michael Stevens

Miaobin Gao

Jesse Chin

Robert Elsheimer

Myunghee Lee

John Michael Page

Song Liu

Vonn Leland Black

Matthew Scott Abrams

Joe Haver

Slawomir K Iinickl

Heng-ju Cheng

Vonn L Black

A result packet generator includes a processor for generation and injection of filtered result packets, at least one counter for determining input/output/result packet bandwidth, and a controller for suppressing generation of the filtered result packets when an output and/or result packet bandwidth and/or a percentage of the result packet bandwidth in the output bandwidth exceeds at least one pre-determined threshold, which may be remotely programmable.

Controlling generation of filtered result packets

In the methods and devices of the present disclosure, a dummy compensation word is added to the data packet such that the UDP checksum value need not be modified from any previous value, regardless of changes to the UDP payload. Because the UDP checksum value is not modified in embodiments of the present disclosure, there is no delay waiting for a UDP checksum value to be calculated and no need for additional buffers to store the data packet contents because of UDP checksum calculations. The dummy compensation word is calculated so that the unmodified value maintained in the checksum is the checksum for the data packet including the dummy compensation word. By placing the compensation word in the data packet after the last word in the UDP payload, there is no, or very minimal, processing delay and data packet buffering hardware is significantly reduced.

Ethernet UDP checksum compensation

The invention relates to a method and device for configurable parsing of packet headers in a network. A configurable packet header parser (CPHP) includes hard-coded packet header logic implementing a hard-coded state machine and a reconfigurable header parsing logic that is coupled to the hardcoded logic and includes programmable registers. The CPHP is remotely programmable by means of a command packet parser that may receive command packets carrying CPHP configuration data and program the registers with the CPHP data to enable parsing packet including new types of headers. The hybrid hard-coded/programmable CPHP requires only a relatively small number of programmable elements enabling ASIC-based implementation.

Reconfigurable packet header parsing

A method of network testing relies on communication with an unaddressed test device. The method includes collection of network addresses from packets passing through the test device and a discovery procedure. The collected addresses are provided to a remote control device, and used for communication between the test device and the control device.

Network communication at unaddressed network devices

A test device includes a packet input receiver for receiving encapsulated packets from a network; a packet reader for extracting timing information from the encapsulated packets, and for decapsulating encapsulated packets so as to obtain test packets; a FIFO queue for storing the test packets; a packet controller for reading the test packets from the FIFO queue and writing the test packets into a de-jitter buffer in accordance with the timing information, the de-jitter buffer for storing the reordered test packets; and, a packet output generator for providing the test packets to a target device wherein time intervals between the test packets are reproduced using the timing information.

Method of remote active testing of a device or network

A communications apparatus includes an input for receiving a data stream being transmitted from a first network node to a second network node using a main channel. A processing resource of the communications apparatus identifies data signifying an idle period within the data stream and determines whether the idle period is at least a suitable minimum duration to support initiating transmission of sub-channel data in place of at least part of the data signifying the idle period. Further, the processing resource is arranged to identify when the idle period is not of the suitable minimum duration and a need arises to transmit the sub-channel data within a predetermined period of time. In such circumstances, the processing resource sends a flow control message upstream to the first network node to halt transmissions therefrom, thereby generating the idle period of at least the suitable minimum duration.

Communications system, apparatus for creating a sub-channel and method therefor

Apparatus for making legacy network elements transparent to IEEE 1588 Precision Time Protocol operation. Network elements are wrapped by device(s) capable of providing either transparent clock or boundary clock operation. In one embodiment, smart interface converters are used to provide transparent clock or boundary clock operation. The smart interface converters work cooperatively.

Method and apparatus for establishing IEEE 1588 clock synchronization across a network element comprising first and second cooperating smart interface converters wrapping the network element

Aspects of the disclosure embody a multi-master two-wire serial bus that comprises two or more chained two-wire serial busses. The chained two-wire serial busses include a host two-wire serial bus with a first master device and one or more slave devices. One or more chained two-wire serial busses are coupled to the host bus wherein one or more slave devices on the host two-wire serial bus operate as second master devices, which comprise a digital state machine including a two-wire serial slave component coupled to the master device and a two-wire serial master component coupled to the slave devices on the chained two-wire serial bus. The digital state machine emulates a slave device on the host two-wire serial bus and a master device on the chained two-wire serial bus.

Multi-master, chained two-wire serial bus

A communication module includes a switch circuit operable to connect an internal bus to an external bus for, e.g., diagnostics, verification, and fault analysis. The internal bus allows data communication between electronic components internal to the communication module, and the external bus allows data communication between at least one internal electronic component and a device external to the communication module. The switch circuit may be controlled via a programmable and password protected register within the communication module.

Switch for coupling one bus to another bus

A circuit for disabling an energy-generating component. The circuit comprises an input operable to receive a disable signal and a disable circuit operable to disable the component in response to the disable signal for a predetermined duration of time sufficient to maintain an average power generated by the component at or below a predetermined level. The disable circuit further comprises a signal-detection circuit operable to detect the presence of disable signals having a respective rising edge and falling edge, a mask-signal generating circuit coupled to the signal detection circuit and operable to generate a mask signal when one of the edges of a first disable signal is detected; and a latching circuit coupled to the mask-signal generating circuit and operable to generate a mask disable signal if the mask signal is being generated and the other edge of a subsequent disable signal is detected.

Disable/enable control for laser driver eye safety

A transceiver including a controller, a first memory that includes first information, and a second memory accessible by a host is provided. The controller is configured to copy the first information from the first memory to the second memory.

EEPROM emulation in a transceiver

A module that detects a password at a hidden address in order to implement a change in an address scheme. The module includes a bus and a memory having a memory address which is coupled to the bus. The module further includes an interface-comparing circuit that monitors data traffic on the bus and receives a predetermined password. The module still further includes a password-comparing circuit which is coupled to the interface-comparing device and allows access to the memory in response to the interface-comparing circuit receiving the proper predetermined password. Such a module can implement a change in the module's configuration or operating characteristics. Such changes include acknowledging a new memory address into the address scheme, unacknowledging an existing memory address in the address scheme and downloading a new operating program having a new address scheme to a controller coupled to a second bus.

System and method for implementing a hidden address in a communication module

A laser driver for generating drive waveforms that are suitable for driving a single VCSEL or an array of VCSELs. A digital controller is integrated into the laser driver and is utilized to initially program and selectively adjust during the operation of the driver one or more of the following VCSEL drive waveform parameters: (1) bias current, (2) modulation current, (3) negative peaking depth, and (4) negative peaking duration. The laser driver has an aging compensation mechanism for monitoring the age of the laser and for selectively adjusting the dc and ac parameters of the VCSEL drive waveform to compensate for the aging of the laser. The laser driver also has a temperature compensation mechanism for monitoring the temperature of the driver IC and selectively adjusting the dc and ac parameters of the VCSEL drive waveform to compensate for the changes in temperature.

Open-loop laser driver having an integrated digital controller

A system that includes a first circuit configured generate a first set of encoded signals in response to a first clock signal and a second circuit configured to generate a second set of encoded signals in response to the first clock signal is provided. The system also includes a third circuit configured to generate a first pulse signal and a second pulse signal in response to the first set of encoded signals and the second set of encoded signals, and a fourth circuit configured to generate a second clock signal in response to the first pulse signal and the second pulse signal.

Growing community of inventors

Palo Alto, CA, United States of America

Takashi Hidai