Fujitsu Semiconductor Limited

Cypress Semiconductor Corporation

Socionext Inc.

Takashi Hanai

Shinichi Sutou

Tetsuo Kawano

Masaki Arai

Ichiro Kasama

Mitsuharu Wakayoshi

Kiyomitsu Katou

Takahiro Kubota

Kyoji Sato

Junji Sahoda

Hayato Higuchi

A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction.

Reconfigurable circuit having rows of a matrix of registers connected to corresponding ports and a semiconductor integrated circuit

A reconfigurable integrated circuit device includes plural processing elements each including an arithmetic circuit, and being configured in any computing state based on the configuration data; and an inter-processing element network which connects the processing elements in any state based on the configuration data. And the processing element inputs an input valid signal and an input data signal, and outputs an output valid signal and an output data signal, and includes an input data holding register, an arithmetic processing circuit, and an output data holding register which holds the computing result data, and when the configuration is updated by configuration data which makes a hold mode valid, regardless of the input valid signal, valid or invalid, the input data holding register holds the input data signal upon the update and the arithmetic processing circuit performs computing processing on the input data signal held in the input data holding register.

Reconfigurable integrated circuit device

A reconfigurable circuit includes a reconfigurable arithmetic execution unit array including a plurality of arithmetic execution units and a network circuit to provide reconfigurable connections between the arithmetic execution units, a suspension control circuit configured to control suspension and resumption of operation of the reconfigurable arithmetic execution unit array, and a buffer circuit configured to temporarily store data supplied from an external source upon suspension of the operation of the reconfigurable arithmetic execution unit array and to supply the stored data to the reconfigurable arithmetic execution unit array upon resumption of the operation of the reconfigurable arithmetic execution unit array.

Reconfigurable circuit with suspension control circuit

An integrated circuit according to the invention includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, and an input data controlling section. The input data controlling section controls input data such that the data is inputted to the reconfigurable circuit in response to a configuration of the reconfigurable circuit.

Integrated circuit and input data controlling method for reconfigurable circuit

A dynamic reconfigurable circuit includes multiple clusters each including a group of reconfigurable processing elements. The dynamic reconfigurable circuit is capable of dynamically changing a configuration of the clusters according to a context including a description of processing of the processing elements and of connection between the processing elements. A first cluster among the clusters includes a signal generating circuit that when an instruction to change the context is received, generates a report signal indicative of the instruction to change the context; a signal adding circuit that adds the report signal generated by the signal generating circuit to output data that is to be transmitted from the first cluster to a second cluster; and a data clearing circuit that, when output data to which a report signal generated by the second cluster is added is received, performs a clearing process of clearing the output data received.

Multi-cluster dynamic reconfigurable circuit for context valid processing of data by clearing received data with added context change indicative signal

A reconfigurable circuit includes a network circuit for controlling connections between the output terminal and the input terminal of an arithmetic unit group, and a first selector connected between the arithmetic unit group and the network circuit. When a first control signal is in a first state, the first selector connects a first terminal of the arithmetic unit group to a first terminal of the network circuit, and also connects a second terminal of the arithmetic unit group to a second terminal of the network circuit. Meanwhile, when the first control signal is in a second state, the first selector connects the first terminal of the arithmetic unit group to the second terminal of the network circuit, and also connects the second terminal of the arithmetic unit group to the first terminal of the network circuit.

Reconfigurable circuit

A dynamic reconfigurable circuit that implements optional processing by dynamically switching a processing content of a reconfigurable processing element (PE) and a connection content between the PEs in accordance with a context, includes: a configuration register section for setting a content of loop processing on the basis of the context, the loop processing content including an output source of an output signal from each of a set of the reconfigured PEs, an output destination of the output signal, and a condition for outputting the output signal to the output destination; and at least one counter circuit including a loop control section and an output register section that implement the set loop processing, that count the number of implementations of the loop processing implemented by the loop control section, and that output the output signal to the output destination based on the counted number of implementations and the condition.

Growing community of inventors

Kawasaki, Japan

Takashi Hanai