Hokkaido University

Sharp Kabushiki Kaisha Corporation

Japan Science and Technology Agency

Honda Motor Co., Ltd.

Takashi Fukui

Katsuhiro Tomioka

Junichi Motohisa

Hajime Goto

Tomotaka Tanaka

Kenji Hiruma

Shinjiroh Hara

Shinjiro Hara

The present invention pertains to a group III-V compound semiconductor nanowire able to be used in a group III-V compound semiconductor MOSFET (FET) operational at a small subthreshold (100 mV/dec or less). A side face of the group III-V compound semiconductor nanowire is a (&#x2212;110) plane constituted of a very small (111) plane. The group III-V compound semiconductor nanowire has, e.g., a first layer having a (111)A plane as a side face thereof, and a second layer having a (111)B plane as a side face thereof. The first layer and the second layer are stacked alternatingly in the axial direction.

Group III-V compound semiconductor nanowire, field effect transistor, and switching element

The tunnel field effect transistor according to the present invention has: a channel; a source electrode connected directly or indirectly to one end of the channel; a drain electrode connected directly or indirectly to the other end of the channel; and a gate electrode for causing an electric field to act on the channel, generating a tunnel phenomenon at the source electrode-side joint part of the channel, and simultaneously generating a two-dimensional electron gas in the channel.

Tunnel field effect trasnsistor

A tunnel field-effect transistor (TFET) is configured by disposing a III-V compound semiconductor nano wire on a (111) plane of a IV semiconductor substrate exhibiting p-type conductivity, and arbitrarily disposing electrodes of a source, drain and gate. Alternatively, the tunnel field-effect transistor is configured by disposing a III-V compound semiconductor nano wire on a (111) plane of a IV semiconductor substrate exhibiting n-type conductivity, and arbitrarily disposing electrodes of a source, drain and gate. The nano wire is configured from a first region and a second region. For instance, the first region is intermittently doped with a p-type dopant, and the second region is doped with an n-type dopant.

Tunnel field-effect transistor, method for manufacturing same, and switch element

Disclosed is a light emitting element, which emits light with small power consumption and high luminance. The light emitting element has: a IV semiconductor substrate; two or more core multi-shell nanowires disposed on the IV semiconductor substrate; a first electrode connected to the IV semiconductor substrate; and a second electrode, which covers the side surfaces of the core multi-shell nanowires, and which is connected to the side surfaces of the core multi-shell nanowires. Each of the core multi-shell nanowires has: a center nanowire composed of a first conductivity type III-V compound semiconductor; a first barrier layer composed of the first conductivity type III-V compound semiconductor; a quantum well layer composed of a III-V compound semiconductor; a second barrier layer composed of a second conductivity type III-V compound semiconductor; and a capping layer composed of a second conductivity type III-V compound semiconductor.

Light emitting element and method for manufacturing same

Disclosed is a semiconductor device () which comprises a glass substrate (), a lower electrode layer (), an n-type doped polycrystalline silicon semiconductor layer (), a low-temperature insulating film () in which openings () that serve as nuclei for growth of a nanowire () are formed, the nanowire () that is grown over the low-temperature insulating film () and has a core-shell structure, an insulating layer () that surrounds the nanowire (), and an upper electrode layer (). The nanowire () comprises an n-type GaAs core layer and a p-type GaAs shell layer. Alternatively, the nanowire can be formed as a nanowire having a quantum well structure, and InAs that can allow reduction of the process temperature can be used for the nanowire.

Semiconductor device and method for manufacturing semiconductor device

A tunnel field effect transistor is capable of operating at a low subthreshold and is able to be manufactured easily. The tunnel field effect transistor includes a group IV semiconductor substrate having a (111) surface and doped so as to have a first conductivity type, a group III-V compound semiconductor nanowire arranged on the (111) surface and containing a first region connected to the (111) surface and a second region doped so as to have a second conductivity type, a source electrode connected to the group IV semiconductor substrate; a drain electrode connected to the second region, and a gate electrode for applying an electric field to an interface between the (111) surface and the group III-V compound semiconductor nanowire, or an interface between the first region and the second region.

Tunnel field effect transistor and method for manufacturing same

Semiconductor surface emitting elements having a plurality of wavelengths being manufactured on a signal substrate through MOVPE selective growth. More specifically, provided is a semiconductor light emitting element array which comprises; a semiconductor crystal substrate; an insulating film disposed on a surface of the substrate, the insulating film being divided into two or more regions, each of which having two or more openings exposing the surface of the substrate; semiconductor rods extending from the surface of the substrate upward through the openings, the semiconductor rods each having an n-type semiconductor layer and a p-type semiconductor layer being laminated in its extending direction, thereby providing a p-n junction; a first electrode connected to the semiconductor crystal substrate; and a second electrode connected to upper portions of the semiconductor rods; wherein the heights of the semiconductor rods as measured from the substrate surface vary by each of the two or more regions.

Semiconductor light-emitting element array including a semiconductor rod

There is provided a method for producing a multijunction solar cell having four-junctions, the method allowing the area of a device to be increased. On a nucleation site formed on a substrateis grown a semiconductorcomprising the same material as the substratein the shape of a wire. On the semiconductorare successively grown semiconductorsandwith a narrower band gap in the shape of a wire. The semiconductormay be directly grown in the shape of a wire on the nucleation site formed on the substrateIt is preferred to form the nucleation site by forming an amorphous SiOcoatingon the substrateand etching a part of the amorphous SiOcoatingFurther, it is preferred to form an insulating filmin the region except the nucleation sites on the substrateby allowing the amorphous SiOcoatingto remain therein. The semiconductoris GaP; the semiconductoris AlGaAs; the semiconductoris GaAs; the semiconductoris InGaAs; and the semiconductoris InGaAs.

Growing community of inventors

Sapporo, Japan

Takashi Fukui