Seiko Epson Corporation

Takashi Fujise

Junichi Karasawa

Takashi Kumagai

Satoru Kodaira

Satoru Ito

Hisanobu Ishiyama

Kazuhiro Maekawa

Takayuki Saiki

Masahiko Moriguchi

Katsuhiko Maki

Noboru Itomi

Hiroyuki Takamiya

Norimitsu Baba

An integrated circuit device includes at least one data driver block for driving data lines, a plurality of control transistors TCand TC, each of the control transistors being provided corresponding to each output line of the data driver block and controlled by using a common control signal, and a pad arrangement region in which data driver pads Pand Pfor electrically connecting the data lines and the output lines QLand QLof the data driver block are disposed. The control transistors TCand TCare disposed in the pad arrangement region.

Integrated circuit device and electronic instrument

An integrated circuit device includes first to Nth circuit blocks CBto CBN, a first interface region disposed along a fourth side and on the Dside of the first to Nth circuit blocks CBto CBN, and a second interface region disposed along a second side and on the Dside of the first to Nth circuit blocks CBto CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction Dover the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.

An integrated circuit device includes first and second transistors NTrand PTrpush-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node ND by a charge-pump operation, and a pad PD electrically connected with the connection node ND and electrically connected with a flying capacitor, to which a given voltage is applied at one end, at the other end of the flying capacitor. The pad PD is disposed in an upper layer of at least one of the first and second transistors NTrand PTrso that the pad PD overlaps part or the entirety of at least one of the first and second transistors NTrand PTr

An integrated circuit device includes a pad PDx and an electrostatic discharge protection element ESDx formed in a rectangular region and electrically connected with the pad PDx. The pad PDx is disposed in an upper layer of the electrostatic discharge protection element ESDx so that an arrangement direction of the pads is parallel to a long side direction of the region in which the electrostatic discharge protection element ESDx is formed, and the pad PDx overlaps part or the entirety of the electrostatic discharge protection element ESDx.

An integrated circuit device including first to Nth circuit blocks CBto CBN disposed along a first direction D, when the first direction Dis a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction Dis a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CBto CBN include at least one memory block MB which stores image data, and at least one data driver block DB which drives data lines. The memory block MB and the data driver block DB are disposed adjacent to each other along the first direction D

An integrated circuit device includes first to Nth circuit blocks CBto CBN disposed along a direction Dwhen a direction from a first side which is a short side of the integrated circuit device toward a third side opposite to the first side is a direction Dand a direction from a second side which is a long side of the integrated circuit device toward a fourth side opposite to the second side is a direction DAt least one of the circuit blocks on both ends of the circuit blocks CBto CBN is a scan driver block for driving a scan line. Or, the scan driver block SB is disposed along the direction Don the side of the first to Nth circuit blocks in the direction D

An integrated circuit device includes: first to Nth circuit blocks CBto CBN disposed along a direction D, the circuit blocks CBto CBN includes a data driver block DB. A data driver DR included in the data driver block DB includes Q driver cells DRCto DRCQ arranged along a direction Deach of the driver cells outputting a data signal corresponding to image data for one pixel. When a width of each of the driver cells DRCto DRCQ in the direction Dis WD, each of the circuit blocks CBto CBN has a width WB in the direction Dof 'Q&#xd7;WD&#x2266;WB&#x3c;(Q+1)&#xd7;WD'.

An integrated circuit device includes first to Nth circuit blocks CBto CBN disposed along a direction D, a first interface region provided on the Dside of the circuit blocks CBto CBN, and a second interface region provided on the Dside of the circuit blocks CBto CBN. The circuit blocks CBto CBN include a data driver block DB and a circuit block other than the data driver block DB. When the widths of the first interface region, the circuit blocks CBto CBN, and the second interface region in the direction Dare respectively W, WB, and W, the integrated circuit device has a width W in the direction Dof 'W+WB+W&#x2266;W&#x3c;W+2&#xd7;WB+W

An integrated circuit device including first to Nth circuit blocks CBto CBN disposed along a first direction D, when the first direction Dis a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction Dis a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CBto CBN include a logic circuit block LB, a grayscale voltage generation circuit block GB, data driver blocks DBto DB, and a power supply circuit block PB. The data driver blocks DBto DBare disposed between the logic circuit block LB and the grayscale voltage generation circuit block GB, and the power supply circuit block PB.

An integrated circuit device including first to Nth circuit blocks CBto CBN disposed along a first direction D, when the first direction Dis a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction Dis a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CBto CBN include a high-speed interface circuit block HB which transfers data through a serial bus using differential signals, and a circuit block other than HB. The high-speed interface circuit block HB is disposed as an Mth circuit block CBM (2&#x2266;M&#x2266;N&#x2212;1) of the circuit blocks CBto CBN.

An integrated circuit device, including first to Nth circuit blocks CBto CBN disposed along a first direction D, when the first direction Dis a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction Dis a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CBto CBN include at least one memory block MB which stores image data, and at least one data driver block DB which drives data lines; and the memory block MB includes a memory cell array, a row address decoder RD, and a sense amplifier block SAB. The row address decoder RD is disposed so that a longitudinal direction of the row address decoder RD coincides with the direction D, and the sense amplifier block SAB is disposed so that a longitudinal direction of the sense amplifier block SAB coincides with the direction D

A step-down circuit is provided that comprises a clock control circuit which provides a plurality of clock signals having a frequency determined based on a control signal; a charge pump circuit which reduces a first potential applied to a first terminal and then provides a second potential from a second terminal by switching the connection of a plurality of capacitors in sync with a plurality of the clock signals output from the clock control circuit; and a comparator which produces the control signal to be supplied to the clock control circuit by comparing the second potential to a reference potential.

Step-down circuit, power supply circuit, and semiconductor integrated circuit

A semiconductor integrated circuit is provided comprising a first amplifier circuit which receives a first potential and then supplies a current to an output terminal; a second amplifier circuit which receives a second potential and then absorbs a current from the output terminal; and a control circuit which controls the second amplifier circuit so as to allow the second amplifier circuit to be activated subsequently to a predetermined period of time that elapses after the first amplifier circuit is activated.

Semiconductor integrated circuit

A semiconductor integrated circuit comprises a storage device that receives an input of data representative of an image to be displayed on a display apparatus and stores the data in a manner corresponding to a plurality of signal electrodes of the display apparatus, and outputs the stored data from a plurality of output terminals, a signal generation device that generates a plurality of signals to be supplied to the plurality of signal electrodes of the display apparatus based on data input through a plurality of input terminals, and outputs the same from a plurality of output terminals, and a selection device that selects data input from the plurality of output terminals of the storage device according to a selection signal that is externally input, and supplies the same to the plurality of input terminals of the signal generation device.

Growing community of inventors

Shiojiri, Japan

Takashi Fujise