Adaptec, Inc.

Takashi Asami

Thomas R Schneider

Aurelio J Cruz

Khanh Trong Vu

An integrated circuit, configured for connection to an SCSI bus includes a strobe assertion edge triggered glitch filter. Input data latches are controlled by the strobe assertion edge gated with a strobe enable signal and the inverted and delayed Q output of a flip-flop. Once a valid strobe assertion edge is detected, it is used latch data bus signals into the data latches. Following a defined delay period through a delay stage, the data latch strobe is masked from any further transition until the strobe enable signal is again affirmatively asserted by an SR latch. The masking period is defined upon receipt of a valid strobe assertion edge and maintained for a first period by the combination of the SR latch, a flip-flop and a delay stage. The latch strobe mask is maintained for a second period by a strobe masking extension circuit made up of series-connected flip-flops. The strobe mask extension period is determined by a sampling or reference clock frequency which propagates a signal through the flip-flops to subsequently cause the SR latch to affirmatively assert a strobe enable signal just before the expected arrival of a next valid assertion edge of the strobe signal.

Integrated circuit SCSI I/O cell having signal assertion edge triggered

An integrated circuit provides for adjustable slew rate control for both rising and falling edges of an output provided to an SCSI bus. Slew rate is controlled by adaptively varying the charge and/or discharge rate of the gate electrode of an output driver's N-channel pull-down transistor. Charge time and, thus, the falling edge slew rate, is adaptively varied by selectively adding the current source P-channel transistors to a current bus coupled to the gate electrode of the pull-down transistor. Similarly, the discharge rate and, thus, the rising edge slew rate, is adaptively adjusted by selectively switching current sink transistors on to the current bus coupled to the pull-down transistor's gate electrode. The amount of currents sourced or sunk is determined by varying the W/L ratios of both the current source and current sink transistors.

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Mission Viejo, CA, United States of America

Takashi Asami