Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Takashi Arita

Akihiro Goto

Takao Takahashi

Yoshiharu Takahashi

Hirokazu Taki

Satoshi Ookyuu

Yasuhito Suzuki

Hirochika Kawaguchi

Yoshio Matsuda

Shigeo Onoda

Koji Bando

Kiyotaka Nishino

Takaaki Okidono

Akinobu Kawazu

A design support apparatus, when designing multichip packages, verifies connections between a semiconductor chip and leads of a lead frame. Distances between two wires or distances between the wires and the other components are calculated using three-dimensional drawing data (CAD data) and semiconductor package data. Components of the semiconductor packages such as wires, lead frames, or die pads are drawn in the three-dimensional drawing data. The semiconductor package data describes specifications of the semiconductor packages such as outer sizes of the packages. Distance values are compared with design rule data. The design rule data defines constraints on the positional relationship between each wire and each component. The design support apparatus determines whether the acquired positional relationship is proper on the basis of design rule data.

Design support apparatus and method for designing semiconductor packages

The primary objective of the present invention is to select a connecting combination of the plurality of solder ball connection pads and the plurality of wire bond pads, and generate an optimum wiring candidate. For this objective, the wiring pattern generation unit generates a wiring pattern as the information for specifying an in-area wiring route to be wired in each row and an in-area wiring route to be connected to the next row among the solder ball connection pad area closer to the wire bond pad area, based on the design conditions of the wiring route stored in the design condition memory. Then, the wiring plan generation unit generates a wiring plan laying out the plurality of wiring routes by combining the wiring patterns generated for each row, and the wiring rule check unit selects some of the generated wiring plans suited for the wiring rules and generates the plurality of wiring candidates. Furthermore, the quality rating unit rates the generated wiring candidates and selects the best wiring candidate.

Circuit wiring system circuit wiring method semi-conductor package and semi-conductor package substrate

To determine leadframe tip positions, a circular arc portion where leadframe tips are to be arranged is determined so as to be opposed to each of the four corners of a die pad by performing a search. Then, straight line portions are set so as to extend from the circular arc portion and to be opposed to the die pad sidelines. The shape of each leadframe tip on the circular arc portion is defined as a region that is sectioned by two concentric circles and two radial rays extending from the center of the concentric circles. The division between the circular arc portion and straight line portions and the setting of the center of the circular arc portion are performed automatically. The leadframe tip width and interval are determined independently of each other.

Designing method of leadframe tip arrangement

First, a reference point on a die pad and a leadframe tip arrangement line are set. A plurality of isosceles triangles having the same base length are set so that their apices are located at the reference point. A given number of isosceles triangles are arranged inside the leadframe tip arrangement line by adjusting the base length. The base length of the isosceles triangles is employed as a uniform lead pitch, and a uniform lead width is then determined. The base length of the isosceles triangles is calculated by using the successive bisection algorithm.

Leadframe tip arrangement designing method

A designing method calculates leadframe tip arrangement. The method comprises the steps of setting a leadframe tip arrangement region opposed to a die pad sideline of a leadframe, setting a leadframe tip arrangement line in the leadframe arrangement region, and arranging a predetermined number of leadframe tips on the leadframe tip arrangement line at proper intervals. The method allows for the independent calculation of various parameters.

An IC card includes a main substrate and a plurality of sub-substrates. Each sub-substrate has two surfaces on which electronic components are installed. The sub-substrates are mounted on both surfaces of the main substrate within the IC card. Openings in the main substrate receive electronic components installed on the sub-substrates. Such an arrangement makes it possible to provide four layers of electronic components within an IC card.

Growing community of inventors

Hyogo, Japan

Takashi Arita