Mitsubishi Denki Kabushiki Kaisha

Other

Hitachi, Ltd.

Mitsubishi Electric Engineering Company, Limited

Hitachi Ulsi Engineering Corp.

Hitachi Tohbu Semiconductor, Ltd.

Hitachi Hokkai Semiconductor Ltd.

Takashi Araki

Yasuhiro Konishi

Hisashi Iwamoto

Kiyoshi Inoue

Hirotaka Nishizawa

Toshio Sugano

Toshio Yamada

Seiji Sawada

Masamichi Ishihara

Hidetoshi Iwai

Kenichi Yasuda

Yasunori Yamaguchi

Masahiro Yamamura

Seiichiro Tsukui

Jiro Sawada

Tadao Kaji

Yasumitsu Murai

Noboru Shiozawa

Shinobu Takeura

Norihiko Kasai

Ichirou Anjou

Masakatsu Goto

Yoshiaki Anata

Yasushi Sekine

Tetsuji Kohara

Sadao Morita

Tomoyoshi Miura

Mutsuo Tsukuda

To achieve a pseudo experience of launching a shuriken with improved presence feeling. A game device includes: a housing; a light source; an optical mechanism; a movement detection sensor; and a light source driver. The housing is configured to be held on a first palm of an operator. The housing includes a front protruding portion which protrudes forward and an upper surface which faces upward. The light source is housed in the housing and configured to emit light. The optical mechanism is housed in the housing and projects the light from the light source forward from a tip of the front protruding portion. The movement detection sensor detects forward movement of a second palm of the operator on the upper surface, wherein the second palm is different from the first palm. The light source driver drives the light source based on movement detection by the movement detection sensor.

Game device

A control signal generating circuit in a synchronous semiconductor memory device outputs timing signals for controlling activation of a word line and activation of sense amplifier, by delaying an external control signal by prescribed time periods. A bank control signal generating circuit provided for each bank holds activation of the timing signal from the control signal generating circuit, and outputs a signal for controlling timing of activation of the word line and timing of activation of the sense amplifier of the corresponding bank.

Synchronous semiconductor device allowing reduction in chip area by

Semiconductor integrated circuit device, and process and apparatus for

A first clock signal for controlling the inputting of an external signal and for controlling internal operation and a second clock signal for controlling data output are applied to separate clock input nodes, respectively. Data output timing with respect to the first clock signal can be adjusted and thus clock access time and data hold time can be adjusted. Internal data read path is pipelined to include a first transfer gate responsive to the first clock signal for transferring internal read data and a second transfer gate responsive to the second clock signal for transferring the internal read data from the first transfer gate for external outputting through an output buffer. A synchronous semiconductor memory device is provided capable of setting clock access time and data hold time at the optimal values depending on the application and of reducing the clock access time.

Synchronous semiconductor memory device and synchronous memory module

A synchronous semiconductor memory device is provided with a delay circuit between an input latch circuit and a pad. The synchronous semiconductor memory device can operate at a higher speed since respective external input signals supplied to a plurality of pads are delayed such that the time required for transmission from respective pads to the input latch circuit is equal, and that skew is eliminated.

Synchronous semiconductor memory device realizing high speed and

Switches (11, 12) select either of refresh address counters (6a, 6b) in accordance with a refresh bank set signal (.phi.REFADD) when a bank refresh signal (.phi.BANKREF) is activated. An internal bank address (int.BA) serves as the refresh bank set signal (.phi.REFADD) to control the switch (12) and the refresh address counter (6a or 6b) designated by the internal bank address (int.BA) performs a count operation in synchronization with a refresh clock (.phi.REFCLK). The switch (11) outputs either of refresh addresses (Ref.Add.sub.-- A&lt;0:10&gt;, Ref.Add.sub.-- B&lt;0:10&gt;) which is updated. With this configuration provided is an SDRAM which allows access to data during a refresh operation.

Synchronous semiconductor memory device

First and second transistors are connected via a first switch. Second and third transistors are connected in parallel via a second switch. Either an input signal or an output ground voltage is applied to the gate of a third transistor via a third switch. In a LVTTL version, the first switch is on and the second switch is off. By the third switch, the output ground voltage is applied to the gate of the third transistor. As a result, first and second, transistors are arranged in series between the output power supply voltage and the output ground voltage, resulting in an output buffer circuit corresponding to a LVTTL. In a GTL version, the first switch is off and the second switch is on. An input signal is applied to the gate of the third transistor by the third switch. As a result, second and third transistors are arranged in parallel to form an open drain. This can be used as an output buffer circuit corresponding to a GTL.

Output buffer circuit that can be shared by a plurality of interfaces

Growing community of inventors

Hyogo, Japan

Takashi Araki