International Business Machines Corporation

Globalfoundries Inc.

Sony Corporation

Meiji Seika Kaisha, Ltd.

Samsung Electronics Co., Ltd.

Nhk Spring Co., Ltd.

Fuji Photo Film Company, Limited

Meiji Seika Pharma Co., Ltd.

Tokyo Electron Limited

Ulvac, Inc.

Other

Basf Se Corporation

Sony Electronics Inc

Elpis Technologies Inc.

Jrs Corporation

Takashi Ando

Pouya Hashemi

Alexander Reznicek

Choonghyun Lee

Vijay Narayanan

Jingyun Zhang

Hemanth Jagannathan

Martin Michael Frank

Eduard Albert Cartier

Hiroyuki Miyazoe

Reinaldo Ariel Vega

Unoh Kwon

Guy M Cohen

Praneet Adusumilli

Kisik Choi

Lawrence Alfred Clevenger

Ruilong Xie

Bahman Hekmatshoartabari

Tetsuji Yamaguchi

Tenko Yamashita

Seyoung Kim

Paul Charles Jamison

Siddarth A Krishnan

Chih-Chao Yang

Cheng Chi

Kangguo Cheng

Juntao Li

Barry P Linder

Michael Rizzolo

Soon-Cheon Seo

Terence B Hook

Michael Patrick Chudzik

Marwan H Khater

Ruqiang Bao

Renee Tong Mo

Robert H Dennard

Pranita Kerber

Karthik Balakrishnan

Oleg Gluschenkov

Ramachandran Muralidhar

Johnathan E Faltermeier

Sivananda K Kanakasabapathy

Dirk Pfeiffer

Xiao Lin Sun

Robert L Bruce

Kevin K Chan

Isaac Lauer

Injo Ok

Arvind Kumar

Hiroaki Niimi

Peilin Song

Franco Stellari

Matthew Warren Copel

Kevin W Brew

Veeraraghavan S Basker

Keith Kwong Hon Wong

Benjamin David Briggs

Osamu Watanabe

Su Chen Fan

Takashi Watanabe

Teodor Krassimirov Todorov

Vamsi Krishna Paruchuri

John Albrecht Ott

Richard Alan Haight

Jean-Olivier Plouchart

Bruce Bennett Doris

Junli Wang

Ghavam G Shahidi

Chen Zhang

Theodorus E Standaert

Chanro Park

Josephine B Chang

Christian Lavoie

Kern Rim

Jeng-Bang Yau

Joel Pereira De Souza

Takashi Ida

Chandrasekharan Kothandaraman

Herbert Lei Ho

Ravikumar Ramachandran

Wilfried Haensch

Babar Ali Khan

Pranita Kulkarni

Sufi Zafar

Koji Watanabe

Yu Zhu

Kandabara N Tapily

Xin Miao

Ramachandra Divakaruni

Julien Frougier

Cyril Cabral, Jr

Min Gyu Sung

Chung-Hsun Lin

Qing Cao

Nicholas Anthony Lanzillo

Damon B Farmer

Griselda Bonilla

Huiming Bu

Eric Andrew Joseph

Jinping Liu

A transistor structure includes a semiconductor substrate; an NFET channel structure atop the substrate; a PFET channel structure atop the substrate; a first dielectric atop the PFET channel structure; a second dielectric atop the NFET channel structure; a shared internal metal gate atop the dielectrics; a shared ferroelectric layer atop the shared internal metal gate; and a shared external gate electrode atop the shared ferroelectric layer. The first and second dielectrics are doped with different metals that provide differing overall work functions for the PFET and the NFET. A method for making a transistor structure includes depositing a shared dielectric onto an NFET channel structure and a PFET channel structure, and converting the shared dielectric to a first high-k dielectric atop the PFET channel structure and a second high-k dielectric atop the NFET channel structure. The first high-k dielectric and the second high-k dielectric are doped with different metals.

Dielectric tuning of negative capacitance in dual channel field effect transistors

A solid-state switch structure including a first solid-state material having a programable electrical resistance comprising a high electrical resistance obtained following a first type programming pulse and a low electrical resistance obtained following a second type programming pulse, a second solid-state material having a programable electrical resistance comprising a high electrical resistance obtained following said second type programming pulse and a low electrical resistance obtained following said first type programming pulse, a first contact made to a first end of said first solid-state material, a second contact made to a first end of said second solid-state material, a third contact made to a second end of said first solid-state material and to a second end of said second solid-state material.

Solid-state switch

A method of forming a semiconductor device that includes forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure. The method further includes removing the inner sidewall dielectric spacer; and forming a channel epitaxial wrap around layer on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer. The method further includes removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and forming a functional gate structure within the gate opening.

Gate induced drain leakage reduction in FinFETs

A semiconductor structure comprises an active device stack comprising one or more layers, the one or more layers comprising a top electrode. The semiconductor structure also comprises an additional layer disposed over the active device stack, an encapsulation layer surrounding the active device stack and the additional layer, and a contact to the top electrode coupled to the additional layer.

Metal hard mask integration for active device structures

A resistive memory includes: a bottom electrode; a first contact on the bottom electrode; a switching material pad on the first contact, wherein the switching material pad includes an oxide and a plurality of current conducting filaments in the oxide; a top electrode on the switching material pad; a plurality of sacrificial vias contacting the bottom electrode; a second contact that is connected to the bottom electrode; and a third contact that is connected to the top electrode.

Redundant bottom pad and sacrificial via contact for process induced RRAM forming

A memory device including a trench to a first electrically conductive structure; a first electrode of a conformal electrically conductive material contained within the trench in electrical communication with the first electrically conductive structure and is present on sidewalls of the trench; a switching layer is present in the trench on the first electrode and extends outside the trench; and a second electrode present on the switching layer overfilling the trench. The memory device also includes a contact positioned on a portion of the second electrode that is overfilling the trench to provide that the contact is horizontally offset from the first electrode that is present in the trench.

Top contact on resistive random access memory

A semiconductor device includes a first gate-all-around field-effect transistor (GAA FET) device including a first gate stack having first channels and dielectric material including first and second portions having respective thicknesses formed around the first interfacial layers. The semiconductor device further includes a second GAA FET device including a second gate stack having second channels and the dielectric material formed around the second interfacial layers. A threshold voltage (Vt) shift associated with the semiconductor device is achieved based on a thickness of the first portion of the dielectric material.

Gate stack quality for gate-all-around field-effect transistors

Embodiments of present invention provide a method of forming a resistive random-access memory (RRAM). The method includes forming a dielectric layer on top of a supporting structure, wherein the dielectric layer has a bottom electrode embedded therein; forming an oxide layer on top of the bottom electrode; treating the oxide layer in a plasma environment; forming a top electrode on top of the oxide layer; forming a first interlevel-dielectric (ILD) layer on top of the top electrode; forming a via contact and a first metal layer in the first ILD layer, wherein the first metal layer is in contact with the top electrode through the via contact; forming a capping layer on top of the first metal layer through a plasma-enhanced deposition process; and causing formation of one or more filaments in the oxide layer during the plasma-enhanced deposition process. A structure of the RRAM is also provided.

Process-induced forming of oxide RRAM

Embodiments are for vertical field effect transistors having different threshold voltages along the channel. A vertical fin having a vertical channel is formed, one end of the vertical channel including a doped layer, the doped layer causing a threshold voltage at the one end to be different from a remainder of the vertical channel. A source and a drain are formed each coupled to opposite ends of the vertical fin, gate material being formed on the vertical channel.

Vertical transport field effect transistors having different threshold voltages along the channel

A field effect device is provided. The field effect device includes a semiconductor nanosheet segment above a substrate, and a T-shaped inner spacer on the semiconductor nanosheet segment. The field effect device further includes a gate dielectric layer on the semiconductor nanosheet segment, and a first work function material plug on the gate dielectric layer. The field effect device further includes a second work function material layer on the first work function material plug and a center portion of the gate dielectric layer, wherein the second work function material layer is a different work function material from the first work function material plug.

Nanosheet device with T-shaped dual inner spacer

A non-volatile memory apparatus includes a first hydrogen reservoir, which is electrically conductive; a charge of hydrogen, which is captured in the first hydrogen reservoir; a dielectric layer that has a first side that is adjacent to the first hydrogen reservoir and a second side that is opposite from the first hydrogen reservoir; a second hydrogen reservoir that is adjacent to the second side of the dielectric layer, is electrically conductive, and has a side that is opposite from the dielectric layer; and a piezoelectric layer that is adjacent to the side of the second hydrogen reservoir and that has a side that is opposite from the second hydrogen reservoir.

Piezoelectric memory

An approach to forming a semiconductor device where the semiconductor device includes a first power rail that is connected to a decoupling capacitor by way of a first gate. The decoupling capacitor is also connected to a second gate. As such, the decoupling capacitor separates the first gate from the second gate. The decoupling capacitor may include a dielectric liner within a gate cut trench and a ferroelectric material over the dielectric liner. A second power rail may be connected to the decoupling capacitor by way of the second gate. The first gate and the second gate may be inline with respect thereto.

Decoupling capacitor inside gate cut trench

Embodiments of the present invention include a phase change memory (PCM) array. The PCM array may include a plurality of PCM cells. Each PCM cell in the plurality of PCM cells may include a top electrode, a resistive element, and a bottom electrode. The PCM array may also include a global heater surrounding the plurality of PCM cells having a thermally conductive material contacting each of the plurality of PCM cells. The global heater may be configured to receive an electric signal to heat the plurality of PCM cells simultaneously.

Global heater for phase change memory

A semiconductor device comprises a plurality of resistive memory element structures, at least a subset of the plurality of resistive memory element structures being associated with random analog resistive states. The random analog resistive states of the subset of the plurality of resistive memory element structures provide a unique identification of the semiconductor device.

Semiconductor device identification using preformed resistive memory

A semiconductor device including stacked access device and resistive memory includes a stack disposed on a base structure, the stack including an access device stack and a resistive random-access memory (ReRAM) device stack, sidewall spacers disposed along a portion of the stack, a dielectric layer disposed over the stack, the sidewall spacers and the base structure, and an interlevel dielectric disposed on the dielectric layer.

Stacked access device and resistive memory

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Tuckahoe, NY, United States of America

Takashi Ando