International Business Machines Corporation

Globalfoundries Inc.

Sony Corporation

Meiji Seika Kaisha, Ltd.

Samsung Electronics Co., Ltd.

Nhk Spring Co., Ltd.

Fuji Photo Film Company, Limited

Meiji Seika Pharma Co., Ltd.

Tokyo Electron Limited

Ulvac, Inc.

Other

Basf Se Corporation

Sony Electronics Inc

Elpis Technologies Inc.

Jrs Corporation

Takashi Ando

Pouya Hashemi

Alexander Reznicek

Choonghyun Lee

Vijay Narayanan

Jingyun Zhang

Hemanth Jagannathan

Martin Michael Frank

Eduard Albert Cartier

Hiroyuki Miyazoe

Reinaldo Ariel Vega

Unoh Kwon

Guy M Cohen

Praneet Adusumilli

Kisik Choi

Lawrence Alfred Clevenger

Ruilong Xie

Tetsuji Yamaguchi

Tenko Yamashita

Bahman Hekmatshoartabari

Seyoung Kim

Paul Charles Jamison

Siddarth A Krishnan

Chih-Chao Yang

Cheng Chi

Kangguo Cheng

Juntao Li

Barry P Linder

Terence B Hook

Michael Rizzolo

Michael Patrick Chudzik

Marwan H Khater

Ruqiang Bao

Soon-Cheon Seo

Renee Tong Mo

Robert H Dennard

Pranita Kerber

Oleg Gluschenkov

Ramachandran Muralidhar

Johnathan E Faltermeier

Karthik Balakrishnan

Sivananda K Kanakasabapathy

Dirk Pfeiffer

Xiao Lin Sun

Robert L Bruce

Kevin K Chan

Isaac Lauer

Injo Ok

Arvind Kumar

Hiroaki Niimi

Peilin Song

Franco Stellari

Matthew Warren Copel

Veeraraghavan S Basker

Keith Kwong Hon Wong

Benjamin David Briggs

Osamu Watanabe

Su Chen Fan

Teodor Krassimirov Todorov

Takashi Watanabe

Vamsi Krishna Paruchuri

John Albrecht Ott

Richard Alan Haight

Jean-Olivier Plouchart

Bruce Bennett Doris

Junli Wang

Ghavam G Shahidi

Chen Zhang

Theodorus E Standaert

Josephine B Chang

Christian Lavoie

Kern Rim

Jeng-Bang Yau

Joel Pereira De Souza

Takashi Ida

Chandrasekharan Kothandaraman

Herbert Lei Ho

Ravikumar Ramachandran

Wilfried Haensch

Babar Ali Khan

Pranita Kulkarni

Sufi Zafar

Koji Watanabe

Kandabara N Tapily

Yu Zhu

Xin Miao

Chanro Park

Ramachandra Divakaruni

Julien Frougier

Cyril Cabral, Jr

Min Gyu Sung

Chung-Hsun Lin

Qing Cao

Damon B Farmer

Griselda Bonilla

Huiming Bu

Eric Andrew Joseph

Jinping Liu

Xuefeng Liu

Nicholas Anthony Lanzillo

A semiconductor device includes a first gate-all-around field-effect transistor (GAA FET) device including a first gate stack having first channels and dielectric material including first and second portions having respective thicknesses formed around the first interfacial layers. The semiconductor device further includes a second GAA FET device including a second gate stack having second channels and the dielectric material formed around the second interfacial layers. A threshold voltage (Vt) shift associated with the semiconductor device is achieved based on a thickness of the first portion of the dielectric material.

Gate stack quality for gate-all-around field-effect transistors

Embodiments of present invention provide a method of forming a resistive random-access memory (RRAM). The method includes forming a dielectric layer on top of a supporting structure, wherein the dielectric layer has a bottom electrode embedded therein; forming an oxide layer on top of the bottom electrode; treating the oxide layer in a plasma environment; forming a top electrode on top of the oxide layer; forming a first interlevel-dielectric (ILD) layer on top of the top electrode; forming a via contact and a first metal layer in the first ILD layer, wherein the first metal layer is in contact with the top electrode through the via contact; forming a capping layer on top of the first metal layer through a plasma-enhanced deposition process; and causing formation of one or more filaments in the oxide layer during the plasma-enhanced deposition process. A structure of the RRAM is also provided.

Process-induced forming of oxide RRAM

Embodiments are for vertical field effect transistors having different threshold voltages along the channel. A vertical fin having a vertical channel is formed, one end of the vertical channel including a doped layer, the doped layer causing a threshold voltage at the one end to be different from a remainder of the vertical channel. A source and a drain are formed each coupled to opposite ends of the vertical fin, gate material being formed on the vertical channel.

Vertical transport field effect transistors having different threshold voltages along the channel

A field effect device is provided. The field effect device includes a semiconductor nanosheet segment above a substrate, and a T-shaped inner spacer on the semiconductor nanosheet segment. The field effect device further includes a gate dielectric layer on the semiconductor nanosheet segment, and a first work function material plug on the gate dielectric layer. The field effect device further includes a second work function material layer on the first work function material plug and a center portion of the gate dielectric layer, wherein the second work function material layer is a different work function material from the first work function material plug.

Nanosheet device with T-shaped dual inner spacer

A non-volatile memory apparatus includes a first hydrogen reservoir, which is electrically conductive; a charge of hydrogen, which is captured in the first hydrogen reservoir; a dielectric layer that has a first side that is adjacent to the first hydrogen reservoir and a second side that is opposite from the first hydrogen reservoir; a second hydrogen reservoir that is adjacent to the second side of the dielectric layer, is electrically conductive, and has a side that is opposite from the dielectric layer; and a piezoelectric layer that is adjacent to the side of the second hydrogen reservoir and that has a side that is opposite from the second hydrogen reservoir.

Piezoelectric memory

An approach to forming a semiconductor device where the semiconductor device includes a first power rail that is connected to a decoupling capacitor by way of a first gate. The decoupling capacitor is also connected to a second gate. As such, the decoupling capacitor separates the first gate from the second gate. The decoupling capacitor may include a dielectric liner within a gate cut trench and a ferroelectric material over the dielectric liner. A second power rail may be connected to the decoupling capacitor by way of the second gate. The first gate and the second gate may be inline with respect thereto.

Decoupling capacitor inside gate cut trench

Embodiments of the present invention include a phase change memory (PCM) array. The PCM array may include a plurality of PCM cells. Each PCM cell in the plurality of PCM cells may include a top electrode, a resistive element, and a bottom electrode. The PCM array may also include a global heater surrounding the plurality of PCM cells having a thermally conductive material contacting each of the plurality of PCM cells. The global heater may be configured to receive an electric signal to heat the plurality of PCM cells simultaneously.

Global heater for phase change memory

A semiconductor device comprises a plurality of resistive memory element structures, at least a subset of the plurality of resistive memory element structures being associated with random analog resistive states. The random analog resistive states of the subset of the plurality of resistive memory element structures provide a unique identification of the semiconductor device.

Semiconductor device identification using preformed resistive memory

A semiconductor device including stacked access device and resistive memory includes a stack disposed on a base structure, the stack including an access device stack and a resistive random-access memory (ReRAM) device stack, sidewall spacers disposed along a portion of the stack, a dielectric layer disposed over the stack, the sidewall spacers and the base structure, and an interlevel dielectric disposed on the dielectric layer.

Stacked access device and resistive memory

A method for system authentication includes subjecting a system to a challenge. The method further includes receiving a response from the system. The received response is dependent upon a location of a filament in a resistive random-access memory device of the system. Additionally, the response is also a unique identifier.

RRAM filament location for physically unclonable function

A capacitive memory cell includes an electrode, a tunneling barrier layer in direct contact with the electrode, a charge trapping layer in direct contact with the tunneling barrier layer, a ferroelectric layer in direct contact with the charge trapping layer, and another electrode in direct contact with the ferroelectric layer.

Negative capacitance for ferroelectric capacitive memory cell

A method is presented for attaining different gate threshold voltages across a plurality of field effect transistor (FET) devices without patterning between nanosheet channels. The method includes forming a first set of nanosheet stacks having a first intersheet spacing, forming a second set of nanosheet stacks having a second intersheet spacing, where the first intersheet spacing is greater than the second intersheet spacing, depositing a high-k (HK) layer within the first and second nanosheet stacks, depositing a material stack that, when annealed, creates a crystallized HK layer in the first set of nanosheet stacks and an amorphous HK layer in the second nanosheet stacks, depositing a dipole material, and selectively diffusing the dipole material into the amorphous HK layer of the second set of nanosheet stacks to provide the different gate threshold voltages for the plurality of FET devices.

Multi-Vt nanosheet devices

Embodiments of the invention provide a resistive switching device that includes a metal interconnect electrode and a charge-particle-treated memory stack over the metal interconnect electrode. The charge-particle-treated memory stack includes a plurality of layers that includes a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode. The dielectric layer includes a portion of a blanket dielectric layer. The bottom electrode includes a portion of a blanket bottom electrode layer. The charge-particle-treated memory stack further includes a current-conducting filament characteristic that results from charge particle treatments applied while a top surface of the blanket dielectric layer is exposed and a top surface of the blanket bottom electrode is exposed.

Oxide-based resistive memory having a plasma-exposed bottom electrode

Embodiments of the invention are directed to a structure that includes a resistive switching device (RSD). The RSD includes a first terminal having an outer sidewall surface; a second terminal; an active region having a switchable conduction state; and a first protective layer on the outer sidewall surface of the first terminal.

Resistive switching device having a protective electrode ring

A memory, system, and method to improve integration density while maintaining thermal efficiency through a phase change memory cell with a superlattice based thermal barrier. The phase change memory may include a bottom electrode. The phase change memory may also include an active phase change material. The phase change memory may also include a superlattice thermal barrier proximately connected to the active phase change material. The phase change memory may also include a top electrode proximately connected to the superlattice thermal barrier. The system may include the phase change memory cell. The method for forming a phase change memory may include depositing an active phase change material on a bottom electrode. The method may also include depositing a superlattice thermal barrier proximately connected to the active phase change material. The method may also include depositing a top electrode proximately connected to the superlattice thermal barrier.

Phase change memory cell with superlattice based thermal barrier

Growing community of inventors

Tuckahoe, NY, United States of America

Takashi Ando