Hitachi, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Other

Hitachi Displays, Ltd.

Takashi Akioka

Yutaka Kobayashi

Masahiro Iwamura

Kinya Mitsumoto

Masao Shinozaki

Tatsumi Yamauchi

Yuji Yokoyama

Atsushi Hiraishi

Noboru Akiyama

Akira Ide

Shigeru Takahashi

Seigoh Yukutake

Hideaki Uchida

Shinji Nakazato

Nobuyuki Gotou

Hiroki Ueno

Shusaku Miyata

Kenji Nishimoto

Akihisa Aoyama

Yutaka Kohara

Sanae Asari

Hajime Akimoto

Yoshiyuki Kaneko

Yoshiro Mikami

Mitsuru Hiraki

Makoto Tsumura

Nozomu Matsuzaki

Hitoshi Nakahara

Takahiro Nagano

Seigou Yukutake

Masahiro Yamamura

Koyo Katsura

Akihiko Emori

Ryuichi Saito

Hideo Maejima

Takashi Hotta

Atsuo Watanabe

Shigeya Tanaka

Hideo Sawamoto

Akihiro Tamba

Sadayuki Ohkuma

Shuichi Miyaoka

Shuko Yamauchi

Hideo Homma

Tatsuyuki Ohta

Koichi Motohashi

Atushi Hiraishi

Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.

Semiconductor integrated circuit device

An image display device has a display pixel area having plural pixels arranged in a matrix fashion, plural signal lines for supplying display signal voltages to the pixels, and plural pixel selection lines for selecting pixels from among the pixels to be supplied with the display signal voltages. The pixel selection lines include Y-direction selection lines for selecting rows of the pixels arranged in the matrix fashion and X-direction selection lines for selecting columns of the pixels, and the image display device includes a circuit configuration in which the display signal voltages are supplied from the signal lines to only ones of the pixels each having selected simultaneously both of a corresponding one of the Y-direction selection lines and a corresponding one of the X-direction selection lines.

Image display device

An image display displays image data on an image display part constructed by a display pixel array. In an image display in which image data input means for inputting image data so that the display pixel array has two neighboring areas having different frame rates (&#x3e;0) is provided or image data is displayed on an image display part constructed by a display pixel array, there is provided image data input means which can input at least one moving image data and at least one still image data into the image display part at different frame rates (&#x3e;0). A high precision image display can be realized hardly changing a display pixel rewriting speed. A moving image signal output circuit and a still image signal output circuit output image data to the display pixel array, and they are provided as circuit configurations independent of each other.

Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.

Semiconductor memory device

The invention provides a method of producing a semiconductor device conforming to plural supply voltage specifications without increasing the chip size and the production cost, while the device achieves a high-speed performance. The method includes plural processes for forming plural types of MOS transistors supplied with different power supply voltages in correspondence with external power supply voltages, which are comprised of a first process common to the plural types of MOS transistors, a second process following the first process, which is different by each of the plural types of MOS transistors, and a third process following the second process, which is common to the plural types of MOS transistors.

Semiconductor device and method of manufacturing a semiconductor device

Setting means (such as fuse circuits) for adjusting the timings of various signals such as an activation timing of a sense amplifier, a fall timing of a word line, a recovery operation (equalization) of a bit lines and so forth, checking an operation in a test stage of a chip, and permanently programming (fixing) the timing of an internal signal to the condition of the highest operation speed that can be confirmed as acquirable in this check stage, is provided.

High speed semiconductor memory device with short word line switching time

An image display for displaying image data on an image display part constructed by a display pixel array is disclosed. In an image display in which image data input means for inputting image data so that the display pixel array has two neighboring areas having different frame rates (>0) is provided or image data is displayed on an image display part constructed by a display pixel array, there is provided image data input means which can input at least one moving image data and at least one still image data into the image display part at different frame rates (>0). A high precision image display can be realized hardly changing a display pixel rewriting speed.

An information processor having a high performance as a whole is provided by improving the throughput of the processor and the semiconductor memory device. The information processor comprises a memory having a buffer for temporarily holding data and a processor having a memory interface part for controlling the memory to transfer data to the buffer before determining whether the data is to be written in the memory and to write the data in said memory after determining of writing. Data writing and reading to the semiconductor device is pipelined by justifying data exchange between reading and writing. Since the data transfer timings of reading from a memory and writing in the memory can be executed at the same time, the reading process and the writing process can be performed by pipeline-like process and the throughput can be improved.

Semiconductor memory device and information processor using the same

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Akishima, Japan

Takashi Akioka