Nec Electronics Corporation

Takao Yanagida

Takuya Hirota

Satoshi Yamamoto

A semiconductor device (DRAM) according to one embodiment of the present invention includes a plurality of pairs of digit lines (digit True, Not) connected to a memory cell, a common signal line pair (main I/O True, Not) connected to the plurality of pairs of digit lines in common, a main I/O equalizer performing precharge of the common signal line pair, and a control circuit determining whether the precharge operation is continued irrespective of a signal level of a mask signal input from an outside.

Semiconductor device and method of controlling the same

In a conventional equalizer circuit, in an equalizing operation for setting voltages of a wiring pair having a predetermined voltage difference therebetween to be the same, it takes a long time to make the voltages of the wirings in a pair converge to a voltage having an offset with respect to a midpoint voltage of the voltages of the wiring pair after the equalizing operation. According to an equalizer circuit of the present invention, provided is an equalizer circuit () which sets the voltages of a first wiring (SAP) and a second wiring (SAN) to be substantially the same and which has a first transistor (N) connected between the first wiring (SAP) and a first power supply circuit (for example, HVDD&#x2212;Va) and a second transistor (N) connected between the first wiring SAP and the second wiring (SAN). The equalizer circuitmakes the first transistor (N) conductive, and then makes the second transistor (N) conductive.

Equalizer circuit and method of controlling the same

A fuse cutting test method to test the state of a fuse includes measuring the current flowing through the fuse and determining the fuse to be either broken, or not broken, or in a state therebetween, based on the measured current.

Fuse cutting test circuit, fuse cutting test method, and semiconductor circuit

A semiconductor storage device has first and second cell arrays including a plurality of memory cells to store data, a sense amplifier selectively connected with either one of the first and second cell arrays, a first precharge circuit to set a pair of bit lines in the first cell array to a predetermined voltage, a second precharge circuit to set a pair of bit lines in the second cell array to a predetermined voltage, a first switch circuit to connect the sense amplifier with the first cell array, a second switch circuit to connect the sense amplifier with the second cell array, and a switch controller to control conductive state of the first and second switch circuits. In non-selection state where the sense amplifier does not access any of the cell arrays, the switch controller controls one of the switch circuits into conducting state.

Growing community of inventors

Kanagawa, Japan

Takao Yanagida