Panasonic Corporation

Panasonic Ev Energy Co., Ltd.

Matsushita Electric Industrial Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Fujisawa Pharmaceutical Company, Ltd.

Takao Yamamoto

Tetsuya Tanaka

Masaitsu Nakajima

Shinji Ozaki

Norito Yamabe

Ryuta Nakanishi

Hazuki Okabayashi

Keisuke Kaneko

Tokuzo Kiyohara

Tomokazu Sada

Hiroyuki Morishita

Yukikazu Ohchi

Takehisa Hata

Koji Zaiki

Yuji Tokunaga

Masahide Kakeda

Hiroshi Tenmyou

In this power supplying device used in this power storage system, a power supplying unit charges a battery. A control unit controls the power supplying unit so as to charge the battery in a pulsed manner, in at least a part of a charging period of the battery. The control unit extends a unit on time and a unit off time when charging in the pulsed manner, as the temperature of the battery becomes lower.

Power supplying device, power storage system, and charging method

A processor apparatus according to the present invention is a processor apparatus which shares hardware resources between a plurality of processors, and includes: a first determination unit which determines whether or not a register in each of the hardware resources holds extension context data of a program that is currently executed; a second determination unit which determines to which processor the extension context data in the hardware resource corresponds; a first transfer unit which saves and restores the extension context data between programs in the processor; and a second transfer unit which saves and restores the extension context data between programs between different processors.

Processor apparatus and multithread processor apparatus

Provided is a multithreaded processor that can accurately estimate processing time necessary for each thread, and a multithreaded processor that simultaneously executes instruction streams, the multithreaded processor including: a computing unit group that executes instructions; an instruction scheduler that groups the instructions into groups for each of the instruction streams, the instructions being included in the each of instruction streams, and each of the groups being made up of instructions among the instructions to be simultaneously issued to the computing units; an instruction buffer which holds the instructions for each of the groups grouped by the instruction scheduler, the instructions being included in the each of instruction streams; and an issued instruction determining unit that reads the instructions for each of the groups from the instruction buffer in each of execution cycles of the multithreaded processor, and that issues the read instructions to the computing unit group.

Multithreaded processor

In a battery cooling device for cooling a battery with air from a cooling unit, such as a cooling fan, the air flow of the cooling unit is optimally controlled. A air flow control device calculates a calorific value of the battery based on an internal resistance of the battery and a charge/discharge current measured by a current measurement unit, calculates the difference as a differential temperature between battery temperature measured by a battery temperature measurement unit and ambient temperature measured by an ambient temperature measurement unit, and controls the air flow of the cooling fan on the basis of the calculated calorific value and the differential temperature.

Battery cooling device, air flow control device, and computer readable medium

In a battery cooling device for cooling a battery with cooling air from a cooling unit, such as a cooling fan, the cooling fan is not to be driven more than necessary. A cooling air flow control unit calculates a battery temperature change rate indicating an amount of change in battery temperature over a predetermined time based on the battery temperature, and if the calculated battery temperature change rate satisfies a predetermined suppression control condition, the cooling air flow of the cooling fan is suppressed regardless of whether or not the battery temperature is at or below a reference temperature.

Battery cooling device, battery cooling air flow control device, and computer readable medium

A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.

Parallel caches operating in exclusive address ranges

A controller for a rechargeable battery and a temperature estimation method and a deterioration determination method for a rechargeable battery enabling an accurate battery temperature to be obtained through calculation. The controller calculates a heat generation amount of Joule heat generated in the rechargeable battery and a heat generation amount of chemical reaction heat generated in the rechargeable battery to calculate the battery temperature of the rechargeable battery based on the calculated Joule heat generation amount and the calculated chemical reaction heat generation amount. When a cooling device is connected to the rechargeable battery, the controller preferably calculates the battery temperature of the rechargeable battery using the Joule heat generation amount, the chemical reaction heat generation amount, and a value indicating the cooling capability of the cooling device.

Controller for rechargeable battery and temperature estimation method and deterioration determination method for rechargeable battery

The cache memory in the present invention is an N-way set-associative cache memory including a control register which indicates one or more ways among N ways, a control unit which activates the way indicated by said control register, and an updating unit which updates contents of said control register. The control unit restricts at least replacement, for a way other than the active way indicated by the control register.

N-way set associative cache memory and control method thereof

In branch prediction in accordance with the present invention, in order to reduce the storage capacity for storing branch prediction information and simplify an information retrieval circuit while minimizing reduction in branch prediction accuracy, the position of an instruction is stored in advance and an instruction is decoded for execution, the relative position of the instruction decoded for execution is obtained on the basis of the position of the stored instruction, and when the decoded instruction is a branch instruction the result of branch by the branch instruction is recorded as history information in correspondence with the relative position of the branch instruction. After this, an instruction is pre-decoded before execution, the relative position of the pre-decoded instruction is obtained on the basis of the position of the stored instruction, when the pre-decoded instruction is a branch instruction the history information corresponding to the relative position of the pre-decoded branch instruction is referred to, and the result of the execution of the pre-decoded branch instruction is predicted by using the result of the reference to the history information.

Branch prediction method and processor using origin information, relative position information and history information

A processor for controlling execution of instructions stored in a main storage and interruption processing, comprises: interruption processing control device operable to accept an interruption request, analyze an accepted interruption to obtain a cause of the interruption, and generate information indicating a storage position in the main storage of a procedure for processing the cause of the interruption; specific address holding device operable to hold first address information obtained from the information generated by the interruption processing control device; and instruction execution control device operable to decide whether or not the first address information held by the specific address holding device is to be used as information indicating a storage position of an instruction to be executed and control instruction execution according to a decision result.

Processor

The present invention relates to liposome preparations. In particular, the present invention relates to Adriamycin-entrapped liposome preparations comprising cholesterol derivatives having a negative charge as a liposome membrane constituent. Adriamycin-entrapped liposome preparations have many uses in the medical field such as maintaining high Adriamycin blood levels over a long period of time and reducing systemic toxicity, for example.

Growing community of inventors

Osaka, Japan

Takao Yamamoto