Panasonic Intellectual Property Management Co., Ltd.

Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Ricoh Company, Ltd.

Sanyo Electric Co., Ltd.

Olympus Corporation

Olympus Optical Company, Ltd.

Osaka University

Sony Corporation

Olympus Medical Systems Corporation

Anritsu Corporation

Hiroyasu Funakubo

Panasonic Intellectual Property Corporation of America

Takao Yamaguchi

Atsushi Yoshida

Tomoki Ishii

Junichi Sato

Tomoaki Itoh

Satoru Tokutsu

Ichiro Takei

Takeshi Yamashita

Hiroshi Arakawa

Minoru Etoh

Takeshi Ueda

Masayuki Shono

Hiroki Hamada

Daiji Ido

Shoji Honda

Yuuki Soga

Yoshinori Hayashi

Seizo Suzuki

Shin Aoki

Haike Guan

Hiroyuki Suhara

Magane Aoki

Kenichi Takanashi

Tatsuya Ito

Koichi Ejiri

Satoru Itoh

Taira Kouchiwa

Koji Hirakura

Hideo Niko

Takeaki Nakamura

Yasuhito Kura

Katsuji Aoki

Koji Taniguchi

Takahiro Kishi

Kazushi Mori

Ichiro Nakamura

Yosuke Yoshimoto

Yasuyuki Futatsugi

Masakazu Higuma

Nobuyuki Ichiguchi

Tomoyuki Sasaki

Akira Kamogawa

Kazutaka Nakatsuchi

Satoshi Obika

Atsushi Tajiri

Noriyuki Iwata

Hidetoshi Saito

Seiya Miyazaki

Yutaka Tatsuno

Hiroshi Hanafusa

Susumu Aono

Jun Hiroya

Keiichi Yodoshi

Wei Zhang

Hideo Nikoh

Akio Nakano

Minoru Takazawa

Norio Kobayashi

Yuji Sato

Kunio Nobori

Masahiro Fujita

Masami Shimizu

Naoki Miyatake

Yoshinori Matsui

Kiichiro Nishina

Makoto Inoue

Masashi Takeda

Hitoshi Karasawa

Manabu Nakamura

Tetsumaru Kubota

Mitsumasa Okada

Hirofumi Yamamoto

Takashi Yamada

Satoshi Takekoshi

Hiroaki Kinoshita

Mitsuaki Matsumoto

Hideki Noma

Tatsuya Yamaguchi

Atsushi Goto

Nobuaki Ono

Hiroyuki Doi

Akira Fukumoto

Masahiro Hagihara

Akira Ibaraki

Nobuyoshi Yazawa

Yoshifumi Yonemoto

Takenobu Aoshima

Tadao Toda

Fuminori Tanahashi

Masahiro Hamada

Hiroyuki Kuroda

Harumine Yoshiba

Masami Itoh

Reiko Waki

Masahiko Horiba

Kenichiro Ueki

Kiyoshi Tsuji

Katsuya Muramatsu

Takao Inoue

Noritoshi Inoue

Disclosed are a 5′-modified nucleoside and a nucleotide using the same. The nucleoside of the present invention is represented by the formula (I) below. The 5′-modified nucleoside of the present invention is usable as a substitute for a phosphorothioate-modified nucleic acid, which has a risk of, for example, accumulation in a specific organ. The 5′-modified nucleoside also has excellent industrial productivity because a diastereomer separation step is not involved in the production process thereof.

5'-modified nucleoside and nucleotide using same

Provided is a balance-unbalance converter including: a substrate; an unbalanced line; a first balanced line; and a second balanced line on the substrate. The unbalanced line has a first end at which an unbalanced signal is input, and an opened second end. The first balanced line is in parallel with a line portion of the unbalanced line from the first end to a midpoint of the unbalanced line, and has a midpoint-side third end at which a balanced signal is output, and a grounded fourth end. The second balanced line is in parallel with a line portion of the unbalanced line from the second end to the midpoint, and has a midpoint-side fifth end at which the balanced signal is output, and a grounded sixth end. The unbalanced line is bent at the midpoint toward an opposite side of the first and second balanced lines.

Balance-unbalance converter and semiconductor integrated circuit having the same

A method for controlling an information terminal, including: (a) causing a display of the information terminal to display a first screen that includes a message recommending an action that leads to a reduction in a power consumption amount of a facility; and (b) causing the display to display a second screen that prompts an operator to execute an input operation for adjusting the frequency at which (a) is executed, in which, when the input operation is executed, (a) is executed at the frequency adjusted according to the input operation.

Method for controlling information terminal, and information system

An information terminal control method includes: (a) predicting whether an amount of power consumption in a shop exceeds a target value; (b) when the amount of power consumption in the shop is predicted to exceed the target value, causing a display of an information terminal to display a screen displaying a time period during which the amount of power consumption in the shop is predicted to exceed the target value; and (c) causing the display to display a screen displaying a message that presents an action to reduce the amount of power consumption in the time period.

Information terminal control method and energy conservation support system

A bus control device () includes a storage () that stores a transmission order of data pieces transmitted from a first node () to each second node (); a sorter () that receives data pieces transferred from each second node toward the first node and refers to a predefined sorting rule to determine a sorting destination of each data piece; a buffer () that stores the sorted data pieces while classifying the sorted data pieces by the second node as a transmission source; and a connection controller () that refers to change permission/rejection information indicating whether or not an order is permitted to be changed while the data piece is transferred from each second node to the first node, and transmits data pieces, the order of which is not changed, from the buffer to the first node in the same order as the transmission order stored on the storage.

Bus control device, relay device, and bus system

An exemplary interface apparatus includes: a header generator which receives, in a first order, a plurality of request headers extracted from a plurality of request packets, generates response headers associated with the request headers, and then stores the response headers so that the response headers are read in the first order; and a header order controller which controls the header generator so that if the plurality of request data have been transmitted to the memory in a second order, the respective response headers are read in the second order.

Interface apparatus and memory bus system

In the bus system, bus interface apparatuses and routers are connected together through packet exchange buses which have been established on the integrated circuit. The bus interface apparatuses are respectively connected to transmission nodes which transmit data of mutually different numbers of bits in one cycle of operation of the bus system. Each of the bus interface apparatuses generates and transmits a packet based on data received from the transmission node connected and header information including size information indicating the number of bits with respect to the transmission node connected. The router analyzes the packet, gets the size information from the header information, determines how to allocate a space in the buffer for storage by reference to the size information gotten, and stores the received packet in the buffer.

Bus interface apparatus, router, and bus system including them

A bus system () for a semiconductor circuit transmits data on a networked bus between a first node and at least one second node via a relay device () arranged on the bus. The bus system () includes a first bus of a low delay and a second bus of a high delay. The first node generates a plurality of packets by attaching, to the data stored in a buffer (), information specifying a priority of transmission. The relay device () converts a priority based on a priority conversion rule, which is determined based on a transmission delay of the high-delay bus, allocates a buffer of a destination relay device to which each packet is to be sent, based on the converted priority, and sends packets in a descending order. The relay device () stores packets in a buffer () based on the priority.

Bus system and computer program

A power distribution control apparatus includes a power source switcher that switches a power source for supplying electric power to a plurality of load groups between a commercial power source and a battery, control circuitry that controls the power source switcher and a plurality of switches provided in power supply paths between the power source switcher and each of the load groups, and a memory that stores positions of the plurality of switches in the order of priority. When the power source switcher switches to the commercial power source and a power saving time zone in which commercial power consumption is to be reduced is reached, the control circuitry controls the switches to be in a non-conducting state, switches the power source from the commercial power source to the battery using the power source switcher, and sequentially controls the switches in a conducting state in the order of priority.

Power distribution control apparatus, electricity storage system, and power distribution control method

A power control apparatus includes the following elements. A measure measures a value of a current to be supplied from a power supply source to a load set. A switch is disposed on a power supply path from power supply source to a load set. A setter sets a first maximum current value in the case of a normal state in which the load set receives power from a main power supply source and sets a second maximum current value when the load set receives power from the sub power supply source. Control circuitry turns OFF the switch when the value of the measured current exceeds the first maximum current value in the case of the normal state and turns OFF the switch when the load set receives power from the sub power supply source and the value of the measured current exceeds the second maximum current value.

Power control apparatus and control method

A communication device includes: a receiving terminal; a storage device which stores a rule in which a condition regarding a bus system operation environment and an error tolerance scheme are associated with each other, and information regarding a path length; an error processor which determines the error tolerance scheme by utilizing the condition regarding the bus system operation environment and the rule so as to generate error tolerance information corresponding to the received data according to the determined error tolerance scheme; and a sending terminal for sending at least one packet including the error tolerance information and the data to the bus. The operation environment-related condition is a condition for granting an error tolerance for a transmission path of which a bus path length to another communication device, which is a destination of the data, is greater than a predetermined value.

Communication device, router having communication device, bus system, and circuit board of semiconductor circuit having bus system

An exemplary interface apparatus according to the present disclosure connects together an initiator and a packet exchange type bus network formed on the integrated circuit. In the bus network, if the initiator has submitted request data with a deadline time specified, the initiator receives, by the deadline time, response data to be issued by a node in response to the request data. The interface apparatus includes: a correcting circuit which corrects the deadline time of the request data according to the timing when the request data has been submitted, thereby generating corrected deadline time information; a header generator which generates a packet header that stores the corrected deadline time information; and a packetizing processor which generates a request packet based on the request data and the packet header.

In a bus control system for a semiconductor circuit, data is transmitted between first and second nodes over a network of buses. The bus controller is connected directly to the first node and includes: a route load detector which detects loads on routes that form at least one of a group of forward routes leading from the first to the second node and a group of backward routes leading from the second to the first node; a candidate route extraction circuit which extracts a candidate route from the group of routes so that loads on the routes that form the group become uniform; a route determining circuit which determines the route to transmit the data based on the candidate route and a predetermined selection rule; and a data communication circuit which transmits the data between the first and second nodes based on header information including route information indicating the route.

Bus controller, bus control system and network interface

Disclosed are bridged nucleosides and nucleotides. The nucleosides of the present invention have a 2',4&#x2032;-bridged structure and are represented by formula I below: An oligonucleotide containing a 2&#x2032;,4&#x2032;-bridged artificial nucleotide of the present invention has a binding affinity for single-stranded RNA comparable to that of known 2&#x2032;,4&#x2032;-BNA/LNA and higher nuclease resistance than LNA. In particular, since the oligonucleotide has a much higher binding affinity for single-stranded RNA than S-oligo, it is expected that the oligonucleotide is applicable to nucleic acid drugs.

Crosslinked nucleoside and nucleotide

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Osaka, Japan

Takao Yamaguchi