Sony Corporation

Takao Terao

Kazushi Sato

Masami Goseki

Yoshiyuki Kunito

Naofumi Yanagihara

Hiroshi Sugawara

Kenji Komori

Satoshi Mitsuhashi

Tetsuo Kaneko

Rajesh Kumar Dixit

Hideki Yoshida

Daisuke Murakami

It is targeted to prevent picture quality deterioration in the output picture information proper to the interlaced scanned picture and that ascribable to interlaced scanning. To this end, a decimating inverse discrete cosine transform unitapplies inverse orthogonal transform to four low-range coefficients in the horizontal direction and eight coefficients in the vertical direction among the respective coefficients of an orthogonal transform block of the compressed picture information of the input high resolution picture.

Picture decoding method and apparatus using a 4&#xd7;8 IDCT

An inverse discrete-cosine transform apparatus that is simple in structure and can yet output pixel data items different in resolution. The apparatus comprises eight inverse discrete-cosine transform multipliers , ten field, compression, inverse discrete-cosine transform multipliers , eight selectors , eight selectors , eight buffers , eight sign multipliers , a control section, eight adders , and eight buffers . The control section controls the selectors , selectors , buffers and sign multipliers in accordance with whether the input discrete-cosine block has been subjected to field division and where the discrete-cosine coefficients are located in the block. One of the values input to the selectors , selectors , buffers and sign multipliers is thereby selected. The value selected is output after added with the plus sign or the minus sign. The adders add the values output from the selectors , selectors , buffers and sign multipliers . The buffers store the values output from the adders

Inverse discrete-cosine transform apparatus

An ATM communications device connected to an ATM network via an optical fiber improving the efficiency of the traffic in the ATM by separating the real-time data communication system and non real-time data communication system. A CPU bus (or a PCI bus) and a real-time signal bus are connected to an MPEG decoder and an MPEG encoder as real-time data processing devices. The CPU bus is connected to a CPU and a memory as non real-time data processing devices. The ATM communications device includes an optical link, a physical layer device, and an SAR (segmentation and reassembly) devices, carries out processing for communication of real-time data such as a video signal between the ATM network and the real-time signal bus, and carries out processing for communication of non real-time data such as computer information between the ATM network and the CPU bus.

ATM communications device

A communication system is disclosed which can transmit a real-time cell and a nonreal-time cell with no jitters caused in the real-time cell. When a real-time cell and nonreal-time cell are outputted at a same timing, a priority control circuit ( ) passes the output timing of nonreal-time ATM cell once and sets in a flag memory ( ) a wait flag indicating that the nonreal-time cell output timing has been passed once. Also, when there is no real-time ATM cell, the priority control circuit ( ) judges whether a wait flag is set in the flag memory ( ), and allows to output one nonreal-time ATM cell when a flag is set.

Communication system and method

An MPEG downdecoder is to be provided which eliminates pixel dephasing with the field DCT mode and the frame DCT mode without detracting from picture characteristics proper to interlaced pictures. To this end, a decimating IDCT unit effectuates 4&times;4 decimating IDCT if the DCT mode is the field mode. If the DCT mode is a frame mode, a decimating IDCT unit effectuates IDCT on the totality of coefficients of a DCT block to separate the coefficients into two pixel blocks associated with interlaced scanning. The decimating IDCT unit executes DCT on the separated two pixel blocks. The low-frequency components of the two pixel blocks are processed with IDCT and the two pixel blocks are synthesized.

Picture decoding method and apparatus

An MPEG downdecoder is to be provided which eliminates dephasing of pixels during motion compensation to prevent deterioration of the picture quality ascribable to motion compensation. MPEG data of a high resolution picture are processed by decimating IDCT devices with 4&times;4 decimating IDCT to decode data of standard resolution picture data. In the case of the field motion prediction mode, a motion compensation device interpolates respective pixels of a macro-block of reference picture data stored in a frame memory to generate a macro-block constituted by pixels of &frac14; pixel precision. In the case of the frame motion prediction mode, a motion compensation device interpolates respective pixels of macro-block of reference picture data stored in the frame memory to generate a macro-block constituted by pixels of &frac14; pixel precision.

Data transmission system and method

A pulse width modulation apparatus outputs an output pulse having an arbitrary width with respect to an arbitrary point in a pulse period. A delay means associated with a pulse cycle have multi-stage delay output means. Before a control pulse CLKP is fed to each of multi-stage delay output means, a delay time for the delay output means can be set. A rising or falling to be latched by a latch means is controlled based on delay control pulses obtained by the delay output means. An output pulse having an arbitrary pulse width with respect to an arbitrary point can be supplied without occurrence of an offset pulse or a blank duration at the start of each pulse duration.

Growing community of inventors

Kanagawa, Japan

Takao Terao