Tohoku University

Globalwafers Japan Co., Ltd.

Takao Sakamoto

Tetsuo Endoh

Koji Izunome

Takashi Ishikawa

Etsuo Fukuda

Kazutaka Kamijo

Moriya Miyashita

A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×10atoms/cmor more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.

Method for producing three-dimensional structure, method for producing vertical transistor, vertical transistor wafer, and vertical transistor substrate

Growing community of inventors

Kitakanbara-gun, Japan

Takao Sakamoto