Sanyo Electric Co., Ltd.

Takao Saeki

Sakae Sugayama

Kazuo Tomizuka

Fumio Sandoh

Masaki Kinoshita

Hiroya Yamamoto

Jun Suzuki

Takashi Iijima

Toshiaki Imai

Yoshinobu Nomura

An automatic gain control circuit for a receive apparatus for a mobile object which automatically controls the gain of a variable gain amplifier amplifying a received signal from an antenna installed in the mobile object and outputting the amplified signal to the receive apparatus. The circuit comprises an intensity detector that detects an intensity of the received signal; a comparator that compares the detected intensity with first and second threshold voltages; and a controller that outputs a control signal for adjusting the gain to the variable gain amplifier based on the comparing results of the comparator so that the gain of the variable gain amplifier has a hysteresis with respect to the intensity of the received signal.

Automatic gain control circuit for receive apparatus for mobile object

Transistors ( ) turn on and off with mutually opposite phase input signals. Capacitors ( ) discharge when the transistors ( ) turn on, and capacitors ( ) are charged by constant current from constant current sources ( ) when the transistors ( ) turn off. As a result, a gradually rising voltage is obtained at the positive input ends of comparators ( ) while the input signals are L. By comparing this with fixed voltages of reference sources ( ), signals having rise timing shifted from input signals by 90&deg; are obtained. The outputs of the comparators ( ) are mutually shifted by 180&deg;, and at the rise of these outputs, an RS flip-flop ( ) is set and reset so that signals delayed in phase by 90&deg; with respect to the input signals are obtained at its outputs.

Phase shift circuit and FM detector circuit

The development time of a linear SASIC is shortened. In a first block region of a semiconductor chip , circuits of the non-master slice layout, or semiconductor elements are formed, and, in a second block region surrounding the first block region, circuits of the master slice layout are placed.

Semiconductor integrated circuit device

To reduce the number of signal lines in the inside of a radio receiver which determines a reference voltage based on data supplied from an external CPU, the first and second reference value data from the external CPU ( ) is supplied to an input section ( ) of a PLL control circuit ( ), and then latched by a latch circuit ( ). The latched data is converted into an analogue reference voltage in D/A converters ( ). The reference voltage is transferred to a radio receiving circuit ( ) to be supplied to comparison circuits ( ) via a single line, respectively, in the inside of the radio receiving circuit ( ).

Radio receiver

A semiconductor integrated circuit is formed on a semiconductor chip (1) and it includes: a plurality of mat regions (A to T) each including a plurality of circuit elements (10 to 13); partition regions (4) for spacing the mat regions (A to T) from each other; and a pair of power supply line (2) and ground line (3) disposed on each of the partition regions (4). An electronic circuit formed on the semiconductor chip (1) includes circuit blocks having different functions but it is designed for a unit of each mat (A to T) not for a unit of each circuit block.

Semiconductor integrated circuit having a pattern layout applicable to

A semiconductor integrated circuit for a radio comprises: a front end circuit block (1) including at least an oscillation circuit (1b) and a mixing circuit (1c), for converting an RF signal to an IF signal; and an IF amplifying circuit block (2) for amplifying the IF signal and limiting an amplitude thereof, and the front end circuit block (1) is covered with shield electrodes (17, 17a, 17b, 17c) connected to a predetermined potential.

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Gunma, Japan

Takao Saeki