Matsushita Electric Industrial Co., Ltd.

Takao Ozeki

Junichi Kato

Masayoshi Nakayama

Toshio Mukunoki

Asako Miyoshi

Akira Sugimoto

Shinichi Hatakeyama

A switch section connects a first wire line aSL to the gate of a first memory transistorand the source of a second memory transistorand a second wire line bSL to the source of the first memory transistorand the gate of the second memory transistorwhen first type data is to be written into a memory cell; and connects the first wire line aSL to the source of the first memory transistorand the gate of the second memory transistorand the second wire line bSL to the gate of the first memory transistorand the source of the second memory transistorwhen second type data is to be written into a memory cell.

Non-volatile semiconductor memory device

A memory cell array includes a memory cell region composed of memory cells and a sample cell region composed of word line sample cells and bit line sample cells. The word line sample cell and the bit line sample cell are formed so that by a voltage applied to word lines and bit lines, charge transfer from the floating gate electrode occurs more easily than the memory cell.

Semiconductor memory device

Growing community of inventors

Takatsuki, Japan

Takao Ozeki