Hitachi, Ltd.

Other

Hitachi Ulsi Engineering Corp.

Hitachi Keiyo Engineering Co., Ltd.

Hitachi Tohbu Semiconductor, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Engineering Co., Ltd.

Hitachi Ulsi

Takao Okubo

Masamichi Kishi

Shigeru Kadowaki

Takashi Kikuchi

Kunihiro Katayama

Takashi Totsuka

Takashi Tsunehiro

Takeshi Suzuki

Takeshi Wada

Kenichi Kaki

Jun Kitahara

Hajime Yamagami

Tsunehiro Tobita

Ryuichi Hattori

Yukihiro Seki

Manabu Saito

Yosio Takaya

Takeshi Furuno

Masashi Wada

Satoru Nakanishi

Shigeru Suzuki

Manabu Inoue

Yasuro Kubota

Hironori Iwasaki

Yasuyuki Fuse

Takehiko Kumagai

A memory apparatus packaged in one package is provided which includes first data terminals, first address terminals, a status terminal, and memory chips integrated in one semiconductor substrate, one of the memory chips being a nonvolatile memory. Each of the memory chips includes data terminals and address terminals. The data terminals of each of the memory chips are connected to the first data terminals, and the address terminals of each of the memory chips are connected to the first address terminals. The status terminal is arranged to output a status signal which indicates when the nonvolatile memory is in a ready status or in a busy status.

Semiconductor memory, memory device, and memory card

A semiconductor memory ( ) comprising a plurality of memory blocks ( and ) provided with a lot of memory cells, a data input/output buffer ( ), and first control means ( ) for controlling the rewriting and reading of data for the memory cells is provided with first storage means ( ) for designating part of the defective memory blocks and detection means ( ) for detecting the access to a defective memory block designated by the first storage means in accordance with an address signal. In this case, when the detection means detects the access to a defective memory, the first control means inhibits the data rewrite operation for the instruction of the data rewrite operation and inhibits the data output operation of the data input/output buffer for the instruction of the data read operation. The inhibiting function makes it possible to provide a memory device having the compatibility with a non-defective semiconductor memory only by combining semiconductor memories having irremediable defects without fixing the levels of specific address input terminals so as to keep the defective memory blocks non-selective.

A semiconductor file system features a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating correspondence between physical and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information. The controller determines a physical sector address. The control section is for controlling input/output of data from/to the external system and for temporarily storing write data into the first nonvolatile memory from the external system in the volatile memory and then transferring the write data from the volatile memory to the first nonvolatile memory.

Flash memory control method and apparatus processing system therewith

A control method and system when a flash memory is used. as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller comprises control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address. The control section is responsive to the interface information, the first management information, and the second management information for controlling input/output of data from/to the external system and for temporarily storing write data into the first nonvolatile memory from the external system in the volatile memory and then transferring the write data from the volatile memory to the first nonvolatile memory. The consecutive address generation means and the sector address storage means output the physical sector address and the consecutively generated addresses to the first nonvolatile memory and the volatile memory when data at the physical sector address is output from the first nonvolatile memory or when data at the physical sector address is input to the volatile memory.

A semiconductor memory (,) comprising a plurality of memory blocks (,and,) provided with a lot of memory cells, a data-input/output buffer (,), and first control means (,) for controlling the rewriting and reading of data for the memory cells is provided with first storage means (,) for designating part of the defective memory blocks and detection means (,) for detecting the access to a defective memory block designated by the first storage means in accordance with an address signal. In this case, when the detection means detects the access to a defective memory, the first control means inhibits the data rewrite operation for the instruction of the data rewrite operation and inhibits the data output operation of the data input/output buffer for the instruction of the data read operation. The inhibiting function makes it possible to provide a memory device having the compatibility with a non-defective semiconductor memory only by combining semiconductor memories having irremediable defects without fixing the levels of specific address input terminals so as to keep the defective memory blocks non-selective.

A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller has a control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address.

Flash memory control method and information processing system therewith

A non-volatile memory, such as a flash memory card, using a rewritable non-volatile memory is provided with an improved write-protect arrangement. The non-volatile memory includes a collectively electrically erasable and writable memory (e.g., a flash memory), a reset IC for generating a power-on reset signal upon turn-on of the power supply, and a card controller for performing control between each flash memory device and a memory card interface. The flash memory is set with a write protect save register written with an address of an area desired to be subjected to write protect, the write protect save register belonging to an attribute area, and a protect range is set from the system. Since the address to be write-protected is itself written in the non-volatile flash memory, the address will continue to be stored, even if the power is turned off. A method for software write protection control is also provided.

Non-volatile memory, memory card and information processing apparatus

A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller comprises control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address.

Information processing system

Compressor/expander circuits which are built in a common semiconductor substrate along with a random access memory unit function so as to realize compression/expansion processes merely through the internal data transfer controls between the circuits and the random access memory unit as based on built-in control unit. This endows the temporary storage of data and the compression/expansion processes hereof with continuities, and achieves higher speeds for the compression/expansion processes.

Single semiconductor substrate RAM device utilizing data

Growing community of inventors

Oume, Japan

Takao Okubo