Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Tokyo Shibaura Electric Co., Ltd.

Takao Ohta

Junichi Ohno

Hiroshi Inoue

Katsutoshi Komeya

Toshiro Usami

Masanobu Ogino

Shoichi Washizuka

Hiroyuki Kamijo

A semiconductor wafer evaluation apparatus, wherein a conductivity detector and a carrier mobility detector are independently arranged so that detections can be made under optimum conditions, respectively. A wafer carrying unit is arranged so as to carry or convey a semiconductor wafer on a carrying path between the two detectors. These components are controlled by a controller. A carrier concentration is calculated from the conductivity and the carrier mobility detected by both detectors. When a partition wall for preventing interference of an electromagnetic wave is provided between the conductivity detector and the carrier mobility detector, interference between the two detectors is further reduced.

Apparatus for measuring the electrical characteristics of a

A defect-recognition processing apparatus converts into a defect image pattern, via a television camera, crystal defects present on the surface of an object under inspection, to process an image signal, by means of an image processing device, which corresponds to the defect image pattern, to measure rectangular images in terms of their length and their ratio between L.sub.Y and L.sub.X (L.sub.Y : a length in a longitudinal direction and L.sub.X : a length in the lateral direction of the wafer) and to detect defects developed on the surface of the aforementioned object.

Defect-recognition processing apparatus

A method for manufacturing a semiconductor device, comprising the steps of forming a monocrystalline silicon layer on a sapphire substrate, ion-implanting silicon and oxygen in a portion of the silicon layer which is in the vicinity of an interface between the substrate and the silicon layer, performing annealing to improve a crystal structure of the portion of the silicon layer in the vicinity of the interface and forming an insulation layer, selectively forming an element isolation region in the silicon layer to obtain an island silicon layer, forming a gate insulation film on the island silicon layer, forming a gate electrode on the gate insulation film, ion-implanting an impurity in the island silicon layer by using the gate electrode as a mask, and annealing a resultant structure to form source and drain regions in the island silicon layer such that bottoms thereof reach a surface of the insulation layer.

Method of fabricating MOS device on a SOS wafer by stabilizing interface

A semiconductor device comprising an insulating substrate such as sapphire and a semiconductor element region formed on the substrate, wherein an insulating layer containing yttrium or a lanthanide element is interposed between the substrate and semiconductor element region. A method of manufacturing a semiconductor device such as MOS/SOS wherein yttrium or a lanthanide element is ion implanted into an interface between the substrate and the semiconductor film formed on the substrate to form an insulating layer containing yttrium or a lanthanide element at the interface.

Implanting yttrium and oxygen ions at semiconductor/insulator interface

.alpha.-Silicon nitride powder which is used as a raw material for the preparation of high strength silicon nitride with additives such as magnesia and yttrium oxide, and other sintered materials suitable for high temperature gas turbine engine components and the like, is prepared by heating a powdered mixture of silica, carbon and metallic silicon in a nitrogen containing atmosphere and then subjecting the material to a heat treatment in an oxidizing atmosphere for decarbonization of said material.

Growing community of inventors

Tokyo, Japan

Takao Ohta