Mitsubishi Denki Kabushiki Kaisha

Nec-mitsubishi Electric Visual Systems Corporation

Other

Nec Corporation

Nec Display Solutions, Ltd.

Takao Nakano

Jun Someya

Yoshiaki Okuno

Kazuhiro Shimotori

Kazuyasu Fujishima

Hideyuki Ozaki

Katsuhiko Asada

Yasuzi Nagayama

Inou Kensuke

Kenji Murakami

Provided is a method for burying a precast pile in which a borehole and a buried precast pile are strongly integrated, the end bearing capacity and the circumferential frictional force of the precast pile are increased, and the extraction resistance strength thereof is improved. Provided is a method for burying a precast pile in which a foaming agent having an expanding effect is added to the cement milk or mortar in advance, whereby the soil cement formed around the base of the precast pile in the borehole is caused to expand.

Method for burying precast pile

An image signal generating unit supplies a single image signal to multiple image display units having different unit numbers. Embedded in the image signal is an index signal designating the image display units on which the image signal is to be displayed. Each image display unit compares its unit number with the index signal to select displayable frames of the image signal, preferably storing and displaying the most recent selected frame. Each image display unit can thereby display a different image. The image signal may have a standard format.

Image signal generating apparatus, image signal transmission apparatus, image signal generating method, image signal transmission method, image display unit, control method for an image display unit, and image display system

The present invention provides a liquid crystal display capable of detecting external light by an optical sensor without providing a window in front of a product. A top face of a liquid crystal display panel () corresponds to a display surface. A light-guiding plate () is disposed on a rear face of the liquid crystal display panel (). A backlight () shown in FIG.is attached to the light-guiding plate (). Light emitted from the backlight () is guided to the display surface of the liquid crystal display panel () by the light-guiding plate (). A reflection sheet () is disposed on a bottom face of the light-guiding plate (). An optical sensor () is attached to a side face of the light-guiding plate () with its light-receiving face facing the inside of the light-guiding plate ().

Liquid crystal display

A liquid crystal display device is provided. An image memory ( ) stores therein input pixel data (R , B , G ) on a frame-by-frame basis. Differencing circuits ( to ) calculate respective difference data ((R &minus;G ), (B &minus;R ), (G &minus;B )) on a pixel-by-pixel basis. Comparator circuits ( ) output a pulse when the difference data is greater than a difference level (DLV). Counter memories ( to ) perform a counting operation each time the pulse is inputted thereto, and output respective counts (FLN_R, FLN_B, FLN_G) after the counting operation for one line. Comparator circuits ( to ) output a pulse to skip flag registers ( to ), respectively, when the respective counts are greater than a skip level. Skip flags (SPF_Ri, SPF_Bi, SPF_Gi) corresponding to a current line are set at &ldquo;1.&rdquo; A gate pulse for the line corresponding to the skip flags &ldquo;1&rdquo; is skipped. This reduces the write time of image data.

Liquid crystal display device

Image signal generating apparatus, image display unit, and control method enabling display of multiple images from a standard image signal

An object is to control a picture display device from an image signal generating device (e.g. a PC) by using only a cable for transferring an image signal without using a USB cable or the like, so as to adjust the chromaticity, brightness, contrast, etc., in the picture display device and also to set r table data and OSD data and to switch the screen size etc. In a picture display control system, screen adjusting control information for adjusting the screen is added to an image signal outputted from an image signal generating device ( ) and sent to a picture display device through an image signal cable, and the picture display device detects the screen adjusting control information from the image signal and adjusts the screen on the basis of the detected screen adjusting control information.

Picture display control system, image signal generating device, and picture display device

An MPU changes the phase of a sampling clock signal by one step for each frame until the change in the phase reaches 360 degrees. An image quality detector portion sequentially receives a digital image signal to detect a maximum one of data about the absolute value of a difference between adjacent pixels in one frame as an image quality judgement data signal. The MPU detects a maximum one of all image quality judgement data to determine a phase at that time as an optimum phase of the sampling clock signal. The MPU then periodically checks image quality on a screen, and makes a real-time correction to the phase of the sampling clock signal if a temperature drift or the like occurs.

Automatic image quality adjustment device adjusting phase of sampling

An apparatus for turning the posture of flat articles (such as envelopes and post cards) can stably clamp and turn a flat article accurately, with a 90.degree. rotation. The turning apparatus has a cone roller that is disposed along a path for transporting the flat articles. A first plurality of idler pulleys are independently mounted to engage and be driven by the conical surface of the roller. A second plurality of idler pulleys are disposed on the upstream side of the conical surface, with respect to the first idler pulley. At least one running belt is stretched between the first and second idler pulleys. The angle between the conical surface and the running belt is small enough to reliably grip and turn the flat article.

Apparatus for turning flat article posture

An MOS dynamic memory device is improved in operation by adding a cell plate voltage control circuit to terminals of the word lines and connected to respective cell plates. In operation, the cell plate is recharged after discharged during with a time which a word line remains driven.

MOS dynamic memory device

The disposed substrate bias generator comprises a capacitor including an electrically insulating film sandwiched between two electrodes one of which is disposed on one main face of a p.sup.- semiconductor substrate through another electrically insulating film, and a first, a second and a third N.sup.+ semiconductor region disposed in spaced relationship on the same main face. The first and second regions form a grounded source and a drain of an MOSFET connected to both its gate and one of the electrodes of the capacitor. The second and third regions form a source and a drain of another MOSFET connected to both its gate and the other main face of the substrate. A signal is applied to the other electrode of the capacitor.

Substrate bias generator

The disclosed semiconductor memory device has a multiplicity of memory cells disposed in rows and columns. Each memory cell includes two transistors extending in the thickness direction of the device for storing and interconnected into a flip-flop, two lateral transistors for performing the reading-out and writing-in operations respectively and two lateral transistors for addressing. Each of the lateral transistors includes an L-shaped emitter opposed to the base and collector of the associated thickness direction transistor lengthwise of the semiconductor substrate involved and also in the direction of thickness thereof.

Semiconductor memory device

The disclosed linear amplifier comprises a grounded N.sup.+ semiconductor substrate on which an N layer is epitaxially grown. The N epitaxial layer includes three separate P diffusion regions. One of the outermost regions is connected to an input terminal and includes an N diffusion region to form an input, common emitter NPN transistor with the epitaxial layer while forming a feedback, common base PNP transistor with the intermediate P diffusion region and epitaxial layer. The remaining P region forms a load, common base PNP transistor with the intermediate P region and epitaxial layer and is connected to an injector terminal. The intermediate P region and N region are connected to an output terminal.

Growing community of inventors

Tokyo, Japan

Takao Nakano