Sanyo Electric Co., Ltd.

Takao Myono

Toshiyuki Ohkoda

Satoru Kaneko

Yoshitaka Onaya

Shuhei Kawai

Akira Uemoto

An inrush current at beginning of operation of a charge pump circuit is reduced to prevent adverse effect on other circuits in a system. Charge transfer MOS transistors are connected in series. One end of each coupling capacitor is connected to each connecting point of the charge transfer MOS transistors. An output from each clock driver is applied on the other end of the respective coupling capacitor. Each clock driver includes a first clock driver and a second clock driver having higher driving capacity than the first clock driver. Each clock driver is controlled so that the first clock driver is put into operation at first and at the end of a predetermined elapsed time it is stopped and the second clock driver is put into operation.

Charge pump circuit

Charge transfer MOS transistors Mand Mat front two stages are constructed of an N-channel type, and charge transfer MOS transistors at rear two stages are constructed of an P-channel type. Inverting level shift circuits Sand Sand non-inverting level shift circuits Sand S, which can produces an intermediate potential are provided. Because of such a configuration, a charge pump circuit which can realize high efficiency and provide a large output current can be realized. In addition, the gate/source voltage Vgs (transistors are in the ON state) of the charge transfer MOS transistors can be uniformed to 2Vdd.

A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and P-type well regions are formed in the second epitaxial silicon layer. P+-type buried layers abutting on bottoms of the P-type well regions and N+-type buried layers abutting on bottoms of the P+-type buried layers and electrically isolating the P-type well regions from the single crystalline silicon substrate are formed. An MOS transistor is formed in each of the P-type well regions and a drain layer of the MOS transistor and each of the P-type well regions are electrically connected.

Charge pump device

In a charge pump device, occurrence of a latch up can be prevented and current capacity can be increased. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, P-type well regions are formed in the N-type epitaxial silicon layer separated from each other, and P-type lower isolation layers and P-type upper isolation layers are formed between the P-type well regions. Then a charge transfer MOS transistor is formed in each of the P-type well regions. The P-type single crystalline silicon substrate is biased to a ground potential or a negative potential.

A latch up in a charge pump device is prevented as well as a withstand voltage of an MOS transistor used in the charge pump device is increased with this invention. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and P-type well regions are formed in the second epitaxial silicon layer separated from each other. A P-type isolation layer is formed between the P-type well regions. A P+-type buried layer is formed abutting on a bottom of each of the well regions, an N+-type buried layer is formed abutting on a bottom of the P+-type buried layer, and a transistor for charge transfer is formed in each of the P-type well regions.

A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and a P-type well region is formed in the second epitaxial silicon layer. A P+-type buried layer is formed abutting on a bottom of the P-type well region, and an MOS transistor is formed in the P-type well region. The MOS transistor has a first source layer N+S of high impurity concentration, a first drain layer N+D of high impurity concentration and a second source layer N&#x2212;S and/or a second drain layer N&#x2212;D of low impurity concentration, which is diffused deeper than the first source layer N+S of high impurity concentration and the first drain layer N+D of high impurity concentration.

High breakdown voltage CMOS device

A three-stage switched capacitor DC-DC converter capable of generating an output boosted voltage in increments of less than power supply voltage. A first stage of the DC-DC converter comprises two capacitors and three switches, which alternate a connection of the two capacitors. The two capacitors are connected in series when charging by turning one of the switches ON, and are connected in parallel when discharging by turning the other two of the switches ON.

Multi-stage switched capacitor DC-DC converter

A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, and a P-type well region is formed in the N-type epitaxial silicon layer. A P&plus;-type buried layer abutting on a bottom of the P-type well region and an N&plus;-type buried layer partially overlapping with the P&plus;-type buried layer and electrically isolating the P-type well region from the single crystalline silicon substrate are formed. And then, an MOS transistor is formed in the P-type well region.

Large current capacity semiconductor device

P type well regions and are formed in N type well regions and respectively. The N type well regions and are formed separately each other. Charge transfer MOS transistors M and M are formed in the P type well regions and respectively. Thus, parasitic thyristor causing latch-up is nor formed.

Control method of charge-pump circuit

A DC&mdash;DC converter capable of generating an output voltage in increments of less than power supply voltage Vdd is provided. A power supply voltage Vdd is provided to a three-stage switched capacitor type DC&mdash;DC converter. A first stage of the DC&mdash;DC converter comprises two capacitors C and C and switches and , that alternate a connection of the capacitors C and C . The capacitors C and C are connected in series when charging by turning the switch ON, while the capacitors C and C are connected in parallel when discharging by turning the switches and ON. Thus a boosted voltage of 3.5 Vdd is obtained from an output terminal

Control method of DC-DC converter

A charge pump circuit of the Dickson type is provided, which circuit is characterized by clock drivers CD and CD for supplying clock pulses to coupling capacitors C -C In other words, it is arranged in such a manner that the rising time and falling time of the clock pulses CLK and CLKB are extended to the extent that the outputs from the clock drivers CD and CD will not cause resonance.

High efficiency charge pump circuit

Charge transfer MOS transistors M and M at front two stages are constructed of an N-channel type, and charge transfer MOS transistors at rear two stages are constructed of an P-channel type. Inverting level shift circuits S and S and non-inverting level shift circuits S and S , which can produces an intermediate potential are provided. Because of such a configuration, a charge pump circuit which can realize high efficiency and provide a large output current can be realized. In addition, the gate/source voltage Vgs (transistors are in the ON state) of the charge transfer MOS transistors can be uniformed to 2 Vdd.

The charge-pump circuit has at least first and second MOS transistors for charge transfer M and M connected in series, first and second capacitors and , a clock driver supplying clock to one end of the second capacitor , first switching means S for connecting the first and second capacitors to a pumping node in series, and second switching means S and S for connecting the first and second capacitors to the pumping node in parallel The clock driver changes the state of clock when both of the first and second switching means turn off.

Charge-pump circuit and control method thereof

A charge-pump circuit has means biasing electrical potential of a substrate of a MOS transistor for control M so that forward direction current does not flow substantially through a,parasitic diode Dp . In the concrete, the substrate of the substrate of a MOS transistor for control M is biased by voltage of a connecting point of the substrate of a MOS transistor for control M and a capacitor at the case that the substrate of a MOS transistor for control M is P-channel type. Thus, it is prevented that a parasitic diode is biased to forward direction in a charge-pump circuit carrying out voltage fluctuation with lower voltage step than power source voltage Vdd so as to carry out normally charge-pump operation.

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Menuma-machi, Japan

Takao Myono