Matsushita Electric Industrial Co., Ltd.

Takao Kashiro

Tatsuro Juri

Chiyoko Matsumi

Masakazu Nishino

Akira Iketani

Tadashi Ono

Susumu Yamaguchi

Hideki Otaka

Shigeru Awamoto

Makoto Goto

Kiyokazu Hashimoto

Eiji Yamauchi

Hisaji Murata

Iwao Hidaka

Yutaka Ohta

Shozo Fujii

Yoshiki Yamamoto

Kenjirou Nakamura

Hidemi Oka

Ken Yasue

Katsuhisa Yano

Katuji Uro

A video signal processing apparatus processes coded data obtained by compressively coding a digitized video signal. The apparatus includes a specific component removing unit for removing specific components in the coded data. The specific component removing unit has a variable-length decoding unit for subjecting the variable-length coded data to variable-length decoding, an inverse quantization unit for inversely quantizing the processing result of the variable-length decoding unit, by using a first quantization matrix, a quantization unit for quantizing the processing result of the inverse quantization unit, by using a second quantization matrix, and a variable-length coding unit for subjecting the processing result of the quantization unit to variable-length coding. Therefore, the data quantity of the variable-length coded data can be reduced without significantly increasing the circuit scale.

Video signal processing apparatus

The digital signal recording apparatus of the invention for recording a video signal on a recording medium, includes: a mode setting section for setting a recording mode, the recording mode being one of a standard recording mode and a long-time recording mode having a longer recording time than that of the standard recording mode; a sampling section for sampling the video signal at a sampling number corresponding to the recording mode set by the mode setting section, the sampling number when the selected recording mode is the long-time recording mode being smaller than the sampling number when the selected recording mode is the standard recording mode; a coding section for coding the video signal sampled by the sampling section at a compression rate corresponding to the recording mode set by the mode setting section, the compression rate when the selected recording mode is the long-time recording mode being higher than the compression rate when the selected recording mode is the standard recording mode; and a recording section for recording the video signal coded by the coding section on a recording medium.

Digital signal recording apparatus for sampling and compressing signals according to various recording modes

A video signal processing apparatus comprising an oscillating unit for outputting a signal of a stable frequency, a counting unit for counting the period of a cycle of a signal supplied from the outside based on the signal output by the oscillating unit, a clock number calculating unit for calculating the number of clocks in a line based on a result of counting by the counting unit, a comparing unit for comparing the number of clocks calculated by the clock number calculating unit with a threshold to decide which is larger, a switching unit for deciding the number of clocks in the next operation by switching to the number of clocks calculated by the clock number calculating unit if the calculated number of clocks is larger than the threshold, or deciding the number of clocks in the next operation by holding the number of clocks in a line in the current operation as it is, and a synchronizing signal generating unit for, based on the number of clocks in operation decided by the switching unit and the signal output by the oscillating unit, generating a synchronizing signal for a video signal, thereby preventing a shake of a frame signal supplied from the outside from directly affecting a synchronizing signal to be generated for a video signal so that a visually adverse shake of image on a TV screen can be suppressed.

Digital signal recording apparatus

The digital processing apparatus includes a high speed response PLL that produces a first clock signal locked on the horizontal synchronization signal included in the video signal input thereto. An analog to digital converter converts the input video signal with respect to the first clock signal into a digitized video signal. A write controller controls a video memory to store the digitized video signal based on the first clock signal. A low speed response PLL produces a second clock signal based on the vertical synchronization signal included in the video signal. A read controller controls the video memory to read out the stored digitized video signal therefrom based on the second control signal. The digital processing apparatus can store and read the digitized video signal to and from the video memory stably, enabling the video signal read from the video memory to be processed effectively and securely.

Digital processing apparatus using two synchronization signals

Each of a plurality of pages of video data are shuffled, each of the pages being composed of a plurality of blocks of data, using a data memory having a memory capacity of one page. The one page data memory temporarily stores data in a current page. A data address generator generates an address of the data memory so that the data in the current page are written into the data memory in a first sequence and the written data are read out from the data memory in a second sequence which is different from the first sequence to thereby shuffle the data in the current page. The data address generator generates the address such that data in a block in the current page is read from a portion of the data memory indicated by the address generated by the data address generator, and such that data in a block in a next page is written into the portion of the data memory indicated by the address generated by the data address generator.

Data shuffling apparatus possessing reduced memory

A first frequency generator generates a first rotation detecting signal having a period which varies in accordance with a rotating speed of a capstan. Second and third frequency generators generate respective second and third rotation detecting signals having periods which vary in accordance with a rotating speed of a supply side reel and a winding side reel. A capstan speed comparison circuit generates an error in accordance with the periods of the first, second and third detecting signals and associated reference periods. A capstan drive circuit is controlled in accordance with the thus generated error.

Capstan controlling apparatus including capstan, supply side reel and

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Kadoma, Japan

Takao Kashiro