Kabushiki Kaisha Toshiba

Sony Corporation

Mitsubishi Heavy Industries Limited

Other

Tokyo Shibaura Denki Kabushiki Kaisha

Seiko Instruments & Electronics Ltd.

Nissin Precision Machines Co., Ltd.

Takao Ito

Kenji Ohsawa

Kiminori Watanabe

Keiji Kurata

Keisuke Matsuoka

Masayuki Ohsawa

Shuhei Dobara

Hayao Kurono

Akira Yamada

Tetsuo Inoue

Nobuyuki Yasuda

Yasuharu Suda

Yuji Ikegami

Takumi Hori

Akira Tsutsumi

Shojiro Komaki

Shunsuke Tanaka

Masayuki Ohta

Hidetaka Kafuku

Hiromu Okamoto

Masao Miyamoto

Shimetomo Fueki

Shigetoshi Nakatake

Masayuki Ayabe

Fumio Watanabe

Hiroki Mitsui

Hisanori Watanabe

Masahiro Kawakita

Koichiro Tanno

Masayuki Osawa

Yuki Matsushima

Hiroshi Kumakura

Junji Suzuki

Muneyuki Haruki

Takafumi Tsuge

A lining method includes fixing a backing strip in a frame shape to a concrete surface of already-placed concrete so that the backing strip protrudes from the concrete surface; disposing a filler inside a frame of the backing strip; making edges of a plurality of lining plates butt against each other at a position of the backing strip to cover the backing strip and the concrete surface; and joining the edges of the lining plates by seal welding.

Lining method and lining

A pit gate includes a gate body which is inserted between a pool portion storing water and a canal portion connected to the pool portion and is configured to change a flow state of the water, and a seal portion () which is accommodated in a groove-shaped accommodation recess formed in the gate body and seals between the pool portion and the gate body. The seal portion () includes a low-rigidity portion () which is relatively easily deformed by a load according to a water pressure from the pool portion side, and a high-rigidity portion () which is provided on the pool portion side of the low-rigidity portion and is not easily deformed relatively by the load.

Pit gate, pit equipment, nuclear power facility, and pit gate installation method

A frame structure using a tube subjected to bending processing by a pushing bending apparatus is provided to solve the problem of a simple body constituting the small-sized interior space. The frame structure forms a plane of frames by bundling a plurality of tubes or bars, each of which is bent to form a waveform of a constant amplitude around a linear axis in a same plane, to contact maximum amplitude portions of the tubes or bars each other, each maximum amplitude portion being in the same position in the longitudinal direction.

Frame structures

A pit gatethat is accommodated in a slotand that seals service water retained in a first pit and a second pit in a watertight manner includes a gate main body; a sealing memberthat is provided on a surface opposite to the slotin a gate main bodyand that seals between the gate main bodyand the slotin a watertight manner; and an upper pressing clamp, an intermediate pressing clamp, and a lower pressing clampthat are provided in the gate main bodyand that moves gate main bodytoward the sealing memberside due to the weight of the gate main bodyitself.

Pit gate, pit equipment, nuclear power facility, and installation method of pit gate

A sequence-pair creating apparatus includes a block placement storing unit that stores information of size of a block bin a block set B and information of block placement, creates a sequence-pair (P, M), serving as a pair of a sequence P and a sequence M of the block b, and further includes a binary relation setting unit that sets, in accordance with the information of block placement and information of size, a binary relation serving as an order relation that indicates a relative configuration between the blocks of a block pair of two blocks and that is derived from a configuration constraint between the blocks extracted from the information of block placement and information of size or designated by an external input, and a total order relation setting unit that sets a series of ranks of the sequences P and M for all the blocks on the basis of the information of block placement and information of size so as to satisfy all binary relations set by the binary relation setting unit.

Sequence-pair creating apparatus and sequence-pair creating method

A lateral high-breakdown-voltage transistor comprises an ndrain region and an nsource region formed in a psilicon substrate, separated from each other, a gate electrode formed on a channel, insulated from the substrate, an n+ drain contact region formed in the drain region, drain wiring electrically connected to the drain region via the drain contact region, a psubstrate contact region formed in contact with the source region, and source wiring electrically connected to the source region and also connected to the semiconductor layer via the substrate contact region. The transistor is characterized in that the substrate contact regions have respective portions made to be in contact with the source wiring, and accordingly laterally extend from inside the contact surface of the source wiring to outside the contact surface.

Lateral high-breakdown-voltage transistor having drain contact region

A lateral high-breakdown-voltage transistor comprises an n drain region and an n source region formed in a p silicon substrate, separated from each other, a gate electrode formed on a channel, insulated from the substrate, an n&plus; drain contact region formed in the drain region, drain wiring electrically connected to the drain region via the drain contact region, a p substrate contact region formed in contact with the source region, and source wiring electrically connected to the source region and also connected to the semiconductor layer via the substrate contact region. The transistor is characterized in that the substrate contact regions have respective portions made to be in contact with the source wiring, and accordingly laterally extend from inside the contact surface of the source wiring to outside the contact surface.

Lateral high-breakdown-voltage transistor

A semiconductor device with an inductance element reduces eddy current in a conductive element and secures required inductance. The semiconductor device includes a semiconductor chip and the inductance element of flat structure formed on a surface of the semiconductor chip. The semiconductor chip is fixed to the conductive element, to form a package. The element has a magnetic material to face the semiconductor chip.

Semiconductor device with inductance element

A lateral high-breakdown-voltage transistor comprises an n drain region and an n source region formed in a p silicon substrate, separated from each other, a gate electrode formed on a channel, insulated from the substrate, an n drain contact region formed in the drain region, drain wiring electrically connected to the drain region via the drain contact region, a p substrate contact region formed in contact with the source region, and source wiring electrically connected to the source region and also connected to the semiconductor layer via the substrate contact region. The transistor is characterized in that the substrate contact regions have respective portions made to be in contact with the source wiring, and accordingly laterally extend from inside the contact surface of the source wiring to outside the contact surface.

A current mirror circuit comprises first and second lateral-type bipolar transistors having first and second conductive films each formed via an insulation film, on the portion of the surface of a base region between an emitter region and a collector region. The first and second emitter regions and the first and second collector regions formed in the surface region of the base region separately from each other. A diode is used as a bias circuit. The diode applies a bias voltage corresponding to the output current of the first transistor, that is, the reference current, to the first and second conductive films of the first and second transistors, so that the width of the channel formed in a base region is changed in accordance with the reference current, and therefore the current amplification rate of each transistor can be maintained at a high value even if a large operation current is supplied.

Semiconductor integrated circuit

A method of manufacturing a semiconductor integrated circuit (IC) includes the steps of forming a polycrystalline silicon layer containing impurities on a semiconductor substrate; forming an oxidation-resistant insulating layer on the polycrystalline silicon layer; simultaneously forming resist patterns for forming a capacitor element and a resistor element on the oxidation-resistant insulating layer; and patterning the oxidation-resistant insulating layer and the polycrystalline silicon layer in sequence using resist patterns.

Semiconductor device and a method of manufacturing a semiconductor device

A differential amplifier circuit of the present invention includes a device ('transistor') having a back gate electrode formed above the base region of a bipolar transistor between the emitter and collector regions. The back gate electrode of one such transistor is connected to the collector or emitter of another transistor in order to provide positive feedback so that the operation of each transistor is enhanced. The operational speed of the transistors is increased and the amplification factor of the differential amplifier circuit is improved to provide stabilized circuit operation. Accordingly, the degree of circuit integration and the operational stability of the differential amplifier are enhanced as compared with a differential amplifier circuit constructed of conventional bipolar transistors or FETs.

Differential amplifier circuit using lateral-type bipolar transistors

A semiconductor protection circuit for protecting an internal circuit from a surge voltage comprises a depletion type PMOS transistor in which its drain is connected to the input/output terminal of the internal circuit. The control terminal is connected to the gate of the PMOS transistor. The control terminal applies a high voltage or low voltage to the gate in accordance with the ON or OFF state of the power of the internal circuit. When the high or low voltage is applied to the gate, the channel of the PMOS transistor is rendered non-conductive or conductive, respectively. The source of the PMOS transistor is grounded via a PN diode and a junction capacitor provided parallel. When a negative surge voltage is applied, the diode is rendered conductive, thereby protecting the internal circuit. When a positive surge voltage is applied, the diode is broken down, thereby protecting the internal circuit. The surge voltage is made small by the capacitor's static capacitance. When the control terminal is in a high potential state, the channel of the PMOS transistor disappears. Therefore, the internal circuit is released from the diode and capacitor. Consequently, during operation of the internal circuit, the parasitic capacitance at the input/output terminal is reduced.

Semiconductor protection circuit and semiconductor protection device

Protection lines are arranged on both sides of and above a signal line, and ground lines are formed outside the protection lines and a ground line is formed above the protection line. A bias circuit is connected to the signal line and protection lines to set the potential of the protection lines equal to that of the signal line and set the impedance of the protection lines low. The signal line processing a small signal, is surrounded by the low-impedance protection lines of the same potential as that of the signal line, and thus crosstalk can be prevented from occurring between the lines, without causing the components of a high-frequency analog signal to attenuate.

Semiconductor integrated circuit device

Disclosed is an optical fiber coupling device which comprises an optical fiber, a coupling member to which the optical fiber is coupled, a coupling means for coupling the optical fiber to the coupling member, and an optical-fiber fixing section for fixing a part of the optical fiber. The optical fiber is coupled only at its forward end to the coupling member. A part of the optical fiber is fixed at a position separated from the forward end of the optical fiber by a specified distance. Thus, the stress applied to the fixed section of the optical fiber is absorbed into a portion of the optical fiber located between the forward end of the optical fiber and the fixed section of the optical fiber fixed by the optical fiber fixing section and which covers the specified distance, thereby to prevent the stress from being applied to the forward end of the optical fiber.

Growing community of inventors

Tokyo, Japan

Takao Ito