Fujitsu Corporation

Other

Spansion Llc.

Advanced Micro Devices Corporation

Fujitsu Vlsi Limited

Nantero, Inc.

Elite Semiconductor Memory Technology, Inc

Eon Silicon Solution Inc.

Cypress Semiconductor Corporation

Takao Akaogi

Yasushi Kasa

Yasushige Ogawa

Hiromi Kawashima

Shouichi Kawamura

Minoru Yamashita

Lee Edward Cleveland

Kiyoshi Itano

Kazuhiro Kurihara

Ali K Al-Shamma

Masanobu Yoshida

Tien-Min Chen

Kendra Nguyen

Tatsuya Kajita

Nobuaki Takashina

Hisayoshi Watanabe

Colin Stewart Bill

Tetsuji Takeguchi

Ryoji Hagiwara

Boon Tang Teh

Jin-Lien Lin

Youseok Suh

Ya-Fen Lin

Tiao-Hua Kuo

Yong K Kim

Johnny C Chen

Michael Achter

Bhimachar Venkatesh

Yong Bae Kim

Sameer Wadhwa

Nian Niles Yang

Zhigang Wang

Richard M Fastow

Yue-Song He

Ravi Prakash Gutala

Nancy S Leong

Guowei Wang

Kazuhide Kurosaki

Chung K Chang

Michael A VanBuskirk

Shigekazu Yamada

Jonathan S Su

Takeo Tatematsu

Jia Luo

Tsutomu Nakai

Yi-Ching Jean Wu

Yider Wu

Sinsuke Kumakura

Tetsuya Chida

Wing Leung

Tony Chan

Fan W Lai

Yi-Hsiu Chen

Thomas T Shieh

Yu-Kuo Yang

Pauling Chen

Coling Stewart Bill

Yasushige Oqawa

Nancy See Loiu Leong

The present disclosure generally relates to circuit architectures for programming and accessing resistive change elements. The circuit architectures can program and access resistive change elements using neutral voltage conditions. The present disclosure also relates to methods for programming and accessing resistive change elements using neutral voltage conditions. The present disclosure additionally relates to sense amplifiers configurable into initializing configurations for initializing the sense amplifiers and comparing configurations for comparing voltages received by the sense amplifiers. The sense amplifiers can be included in the circuit architectures of the present disclosure.

Devices for providing neutral voltage conditions for resistive change elements in resistive change element arrays

Sense amplifiers

A method of controlling verification operations for error correction of a non-volatile memory device includes the following. A tolerated error bit (TEB) number for error correction of the non-volatile memory device is set to a first value to control verification operations in accordance with the TEB number. After at least one portion of the non-volatile memory device is programmed for a specific number of times, the TEB number is changed from the first value to a second value to control the verification operations in accordance with the TEB number, wherein the second value is greater than the first value and is less than or equal to the TEB threshold. The method may be performed while the at least one portion of the non-volatile memory device is programmed and verified.

Method of controlling verification operations for error correction of non-volatile memory device, and non-volatile memory device

A non-volatile memory having discrete isolation structures and SONOS (Silicon Oxide Nitride Oxide Silicon) memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory.

Non-volatile memory having discrete isolation structure and SONOS memory cell, method of operating the same, and method of manufacturing the same

A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line.

Partial local self boosting for NAND

A method of identifying a damaged bitline address in a non-volatile memory device is introduced. The non-volatile memory device includes a memory cell array and a plurality of bit lines crossing the memory cell array. Each bit line has a first end and a second end. The bit lines are divided into a first group and a second group. The method includes applying a source voltage (charging) or ground voltage (discharging) to a specific group of bit lines, testing the bit lines in two testing stages (open-circuit testing and short-circuit testing) by the principle that no damaged bit line can be charged or discharged, and acquiring an address data of a damaged bit line according to a status data stored in a page buffering circuit and related to whether a bit line is damaged, thereby dispensing with a calculation process for estimating the address of the damaged bit line.

Method of identifying damaged bitline address in non-volatile

In a local word line driver of an NOR flash memory and its flash memory array device, the local word line driver is provided for driving a local word line in a sector of a memory array, and the local word line driver has two transistors including a first transistor and a second transistors, and the first and second transistors are NMOS transistors, and thus achieving the effects of reducing the area occupied by circuits on the local word line driver and the die size, and saving the area for the use by memory units.

Local word line driver and flash memory array device thereof

A device, and corresponding method, includes a temperature dependent bias generator to generate a voltage that is applied to a control gate of a sense amplifier. By applying the temperature dependent bias signal to the sense amplifier, a substantially temperature independent discharge time can be achieved at a sense node of a sense amplifier.

Memory device and method thereof

A method for partial local self-boosting of a memory cell channel is disclosed. As a part of memory cell channel partial local self-boosting, an isolating memory cell located on a source side of a program inhibited memory cell is turned off and a gating memory cell located on a drain side of the program inhibited memory cell is used to pass a pre-charge voltage to the program inhibited memory cell to provide a pre-charge voltage to a channel of the program inhibited memory cell. Moreover, a pre-charge voltage is passed to a buffering memory cell located on the source side of the program inhibited memory cell to provide a pre-charge voltage to a channel of the buffering memory cell and the gating memory cell that is located on the drain side of the program inhibited memory cell is turned off. During programming, a program voltage is applied to the gate of the program inhibited memory cell where a channel voltage of the program inhibited memory cell is raised above a level raised by the pre-charge voltage.

Partial local self-boosting of a memory cell channel

The present disclosure adjusts the voltage threshold values of select gates of NAND strings. The select gates of the NAND string can be read, erased, and programmed.

Non-volatile memory device and methods of using

A sense amplifier includes a reference voltage generator for generating a reference output voltage and a core output voltage generator for generating a core output voltage. The core output voltage generator includes a core front-end stage and a core back-end stage or includes a plurality of amplifier transistors each conducting a portion of a core current through a current conducting device such as core cell. The sizes and/or connections of transistors of such components result in high voltage swing and thus high sensitivity of the sense amplifier.

Sense amplifiers with high voltage swing

Non-volatile memory, such as Flash memory, is programmed by writing a window of information to memory. The programmed/non-programmed state of each memory cell may be dynamically determined for each window and stored as an indication bit. These techniques can provide for improved average power drain and a reduced maximum current per window during programming.

Flash memory programming using an indication bit to interpret state

The present invention provides a method for determining program and erase states in flash memory devices. Specifically, one embodiment of the present invention discloses a method for minimizing false detection of states in an array of non-volatile floating gate memory cells. A plurality of word lines are arranged in a plurality of rows. A plurality of bit lines are arranged in a plurality of columns. The method begins by determining a selected bit line that is associated with a column of memory cells. Then, the method continues by biasing a group of word lines at a negative voltage. The group of word lines are electrically coupled to the associated memory cells. The application of negative voltage to the group of word lines limits leakage current contributions from the associated memory cells in the column of memory cells when performing a verify operation.

Method for minimizing false detection of states in flash memory devices

Growing community of inventors

Cupertino, CA, United States of America

Takao Akaogi