Ultramemory Inc.

Nec Corporation

Takao Adachi

Yasutoshi Yamada

Ryuji Takishita

Fumitake Okutsu

Kouji Uemura

Motoaki Saito

Yuji Motoyama

The present invention provides a semiconductor module, a semiconductor member, and a method for manufacturing the same that make it possible to improve heat dissipation efficiency. This semiconductor modulecomprises: a power supply unit; a RAM unit, which is a RAM module having a facing surface disposed so as to face an exposed surface of a logic chipand an exposed surface of the power supply unit, the RAM module being disposed across some of a plurality of logic chip signal terminalsand some of a plurality of power supply unit power supply terminals; and a support substratehaving a power feeding circuit capable of feeding electrical power to the logic chip and to the power supply unit, one main surface of the support substratebeing disposed adjacent to a heat dissipation surface of the RAM unit, which is the surface of the RAM unitopposite the facing surface. The support substrateis electrically connected, using the power feeding circuit, to at least some of logic chip power supply terminalsand the other power supply unit power supply terminals. The support substratehas, at positions overlapping the RAM unit, heat dissipation viasthat penetrate in the thickness direction and come into contact with the heat dissipation surface of the RAM unit

Three-dimensional semiconductor module including system in a package (SIP) with improved heat dissipation efficiency

The present invention provides a semiconductor module capable of improving a bandwidth between a logic chip and a RAM. According to the present invention, a semiconductor moduleis provided with: a logic chip; a pair of RAM unitseach composed of a lamination-type RAM module; a first interposerelectrically connected to the logic chip and to each of the pair of RAM units; and a connection unitthat communicatively connects the logic chip and each of the pair of RAM units, wherein one RAM unitis placed on the first interposer, and has one end portion disposed so as to overlap, in the lamination direction C, one end portion of the logic chip with the connection unittherebetween, and the other RAM unitis disposed so as to overlap the one RAM unitwith the connection unittherebetween, and is also disposed along the outer periphery of the logic chip.

Semiconductor module

The present invention is intended to provide a semiconductor module and a DIMM module that are capable of stably supplying power to a plurality of stacked memory chips, a manufacturing method of the semiconductor module and a manufacturing method of the DIMM module. The semiconductor modulehaving a plurality of memory chipsincludes: a memory substratehaving a power supply circuitexposed on an arrangement surface as one surface of the memory substrate; and at least one memory unitarranged over the arrangement surface of the memory substrate. The memory unitincludes: the plurality of memory chipsstacked together such that a stacking direction D is along the arrangement surface; a through electrodepassing through the plurality of memory chipsin the stacking direction D; and an electrode layerformed on one end surface in the stacking direction D and connected to the through electrodeand the power supply circuit

Semiconductor module, DIMM module, manufacturing method of semiconductor module, and manufacturing method of DIMM module

The purposes of the present invention are: to provide a layered semiconductor device capable of improving production yield; and to provide a method for producing said layered semiconductor device. This layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. In such a configuration, the semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches. The semiconductor chips and the reserve semiconductor chip are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units. The control chip controls the operating states of the semiconductor chips by switching the operating switches of the semiconductor chips, and controls the operating state of the reserve semiconductor chip by switching the operating switch of the reserve semiconductor chip.

Layered semiconductor device, and production method therefor

The objective of the invention is to provide technology allowing data taking a plurality of values to be transmitted and received using one set of coils when sending data through TCI technology using magnetic field coupling. This layered semiconductor device has at least a first semiconductor chip and a second semiconductor chip layered therein, the first semiconductor chip transmitting data in a contactless manner, and the second semiconductor chip receiving, in a contactless manner, the data that has been transmitted. The first semiconductor chip contains: a transmission unit outputting a transmission signal that may acquire, on the basis of the value of the data to be sent, at least 3 types of states representing the value of the data; and a transmission coil converting the transmission signal into a magnetic field signal. The second semiconductor chip contains: a reception coil whereby the magnetic field signal converted by the transmission coil is converted into a reception signal; and a reception unit reconstructing, on the basis of the state of the reception signal, the data that has been transmitted.

Layered semiconductor device and data communication method

A layered semiconductor device capable of improving production yield and a method for producing the layered semiconductor device. The layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. The semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches, and are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units. The control chip controls the operating states of the semiconductor chips by switching the operating switches of the semiconductor chips, and controls the operating state of the reserve semiconductor chip by switching the operating switch of the reserve semiconductor chip.

A semiconductor element that has an element first main surface, an element second main surface that is the reverse surface from the element first main surface, and an element side surface. The semiconductor element is configured from a semiconductor substrate part and an insulating layer part and is provided with: a signal transmission/reception terminal that is provided to the element first main surface and that contacts and can transmit/receive signals to/from an external-substrate signal transmission/reception terminal that is provided to an external substrate that is external to the semiconductor element; and a signal transmission/reception coil that is provided to the element side surface and that, via the element side surface, can transmit/receive signals in a non-contact manner to/from an external-semiconductor-element signal transmission/reception part that is provided to an external semiconductor element that is external to the semiconductor element. The signal transmission/reception coil has: a conductor that is formed inside the insulating layer part; and a conductor that is formed inside the semiconductor substrate part.

Semiconductor element

A CMOS semiconductor integrated circuit device has an n-(p-)MOS element formed on a p-(n-)type semiconductor substrate and a p-(n-)MOS element formed on an n-(p-)type well region. A substrate potential wiring for providing a substrate potential to the p-(n-)type semiconductor substrate and a source potential wiring connected to the source region of the n-(p-)MOS are provided physically independently from each other, and such potential wiring and such source potential wiring are connected with each other with a resistor being interposed therebetween. Thus, the current which flows in transistors during the operating state of related circuits integrated in the substrate is prevented from flowing into the substrate thereby eliminating any such fluctuations of the substrate potential as may otherwise be caused by the operation of the circuits.

CMOS semiconductor integrated circuit device

A wiring formed in the uppermost level of a plastic encapsulated semiconductor device is fixed by connecting it to anchor wirings provided in a lower level via through holes in order to suppress a shear deformation of the uppermost level wiring. The independent wirings are formed in an islandshaped pattern and have no electrical connection to any circuit elements per se.

Plastic package semiconductor device with thermal stress resistant

An integrated circuit is fabricated on a semiconductor substrate and comprises a plurality of component circuits having first and second circuits respectively serving as signal sources and a third circuit serving as a signal destination, an insulating film covering a major surface of the semiconductor substrate, and a plurality of wiring strips formed in the insulating film and having a first wiring strip interconnecting the first circuit and the third circuit and a second wiring strip coupled to the second circuit, in which the first and second wiring strips are arranged to be opposed to one another through the insulating film and in which the first and second wiring strips respectively propagate signals substantially in phase with one another, so that a parasitic capacitance between the first and second wiring strips are drastically decreased, thereby causing the signal propagations to be improved in speed.

Growing community of inventors

Tokyo, Japan

Takao Adachi