Panasonic Intellectual Property Management Co., Ltd.

Panasonic Corporation

Takanori Ueda

Kazuyuki Kouno

Masayoshi Nakayama

Keita Takahashi

Yasuo Murakuki

Yuriko Ishitobi

A memory array includes a resistive memory cell array having a first cell transistor and a resistance change element connected in series and a reference cell array having a second cell transistor and a resistance element connected in series. The second cell transistor of the reference cell array is connected to a reference source line, and the resistance element is connected to a reference bit line. A dummy memory cell is connected to the reference bit line in the memory cell array, and both ends of a resistance change element of the dummy memory cell are short-circuited through the reference bit line.

Nonvolatile semiconductor memory device

A memory cell array includes a plurality of word lines each connected to gates of cell transistors in corresponding ones of a plurality of memory cells, a plurality of first control lines, a plurality of second control lines, a first ground circuit configured to ground the first control lines together in accordance with a first signal, and the first ground circuit includes a plurality of first transistors provided in a one-to-one correspondence with the first control lines, and each including a drain connected to a corresponding one of the first control lines, a first ground line configured to ground sources of the first transistors together, and a first signal line connected to gates of the first transistors to feed the first signal to the gates.

Ground circuitry for semiconductor memory device

A nonvolatile semiconductor memory device includes: a memory cell array having a plurality of memory cells arranged in a matrix; a reference bit line; a reference source line; at least one reference cell including first and second transistors serially connected between these lines; a reference word line connected to the gate of the first transistor; and a reference driver circuit configured to control the gate voltage of the second transistor.

A non-volatile semiconductor memory device includes a plurality of series-coupled fixed resistance elements, a plurality of reference cell transistors, and reference word lines coupled to gates of the reference cell transistors, a first reference data line coupled to one end of a resistance path in which a plurality of fixed resistance elements are arranged, and a second reference data line coupled in common to one ends of the reference cell transistors. The other end of each of the reference cell transistors is coupled to one of coupling points of the fixed resistance elements or the other end of the resistance path.

Non-volatile semiconductor memory device

A main bit line is disposed between a reference main bit line and core main bit lines. A selection transistor disposed between a sub bit line connected to a cell and the main bit line can switch between a conductive state and a non-conductive state independently of other selection transistors. A dummy main bit line can be set to ground potential by a shield grounding section, and can be used as a shield line of the reference main bit line.

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Kanagawa, Japan

Takanori Ueda