Nec Corporation

Nec Electronics Corporation

Sony Corporation

Renesas Electronics Corporation

Sony Group Corporation

Sony Semiconductor Solutions Corporation

Takanori Saeki

Masatomo Eimitsu

Yasushi Aoki

Kaoru Narita

Masashi Nakagawa

Hirokazu Tohya

Tomoyuki Kaneko

Taras Kushta

Yoshinori Tanaka

Atsushi Suzuki

Tomohiro Takahashi

Natsuki Sato

Yukio Fukuzo

Tadashi Iwasaki

Hironobu Konishi

Minoru Nishizawa

Yuiti Takeda

Koichiro Kiguchi

Toshiyuki Tanaka

Kenichi Tanaka

Masayuki Katakura

Yoichi Iizuka

Makoto Tanaka

Masahiro Takeuchi

Koichiro Minami

Miki Takahashi

Tatsuya Shirakawa

Hiraku Takahashi

Hisakazu Nasu

Toshihiro Narisawa

Nobuhiro Ooki

An imaging element with a pixel array that has pixels each including a photoelectric converting section and an analog-to-digital converting section. The analog-to-digital converting section includes a Gray code latch circuit configured to latch a Gray code corresponding to an analog pixel signal read out from the pixels, a code converter configured to code-convert, into a binary code, the Gray code latched in the Gray code latch circuit, a temporary latch circuit configured to temporarily latch a predetermined binary code, and an arithmetic section configured to determine a difference between a binary code for the same bit resulting from code-conversion by the code converter and the predetermined binary code latched in the temporary latch. Data transfer between the Gray code latch circuit and the code converter is processed in parallel.

Imaging element, signal processing method for imaging element, and electronic equipment

A transmission device of the disclosure includes a first selector configured to select one of a first signal and a second signal, and output the selected signal; a second selector configured to select one of an inversion signal of the first signal, the second signal, and an inversion signal of the second signal, and output the selected signal; a first control signal generator configured to generate a first control signal, a second control signal, and a third control signal, based on the first signal, the second signal, and a third signal; a first driver configured to set a voltage of a first output terminal, based on an output signal of the first selector and the first control signal; and a second driver configured to set a voltage of a second output terminal, based on an output signal of the second selector and the second control signal.

Transmission device and communication system

Transmitters and communication systems are disclosed. In one example, a transmitter includes first to third serializers that generate first to third serial signals; a first output section configured to set a voltage of a first output terminal; a first output control circuit configured to control an operation of the first output section on the basis of the first serial signal and the second serial signal; a second output section configured to set a voltage of a second output terminal; a second output control circuit configured to control an operation of the second output section on the basis of the third serial signal and the first serial signal; a third output section configured to set a voltage of a third output terminal; and a third output control circuit configured to control an operation of the third output section on the basis of the second serial signal and the third serial signal.

Transmitter and communication system

A transmitter of the present disclosure includes: an output terminal; a driver that performs transition of a voltage of the output terminal among a plurality of voltages; and a controller that controls the driver to cause transition start timing in one voltage transition in voltage transition among the plurality of voltages to be later than transition start timing in another voltage transition.

A semiconductor circuit apparatus of the present disclosure includes a control circuit controlling a clock signal externally input, a drive circuit performing a switching operation according to a pulse signal provided by the control circuit, a series connection circuit including an inductor element, a switch element, and a capacitive element connected in series between a signal line and a fixed potential node, the series connection circuit forming an LC resonance circuit, and a level detection circuit having an input end connected to the signal line. An output from the level detection circuit is fed back to the control circuit.

Semiconductor circuit apparatus and system equipped with semiconductor circuit apparatus

A transmitting device of the present disclosure include: a first driver that includes a first sub-driver unit which operates on a basis of a first control signal and a second sub-driver unit which operates on a basis of, of the first control signal and a second control signal, a signal selected through a first selecting operation, and is configured to be able to set a voltage at a first output terminal; and a controller that controls the first selecting operation.

Transmitting device, transmitting method, and communication system

An A/D conversion device includes a phase-difference clock generation unit configured to use a plurality of phase interpolators to generate multi-phase clock signals, of which phases are shifted with respect to an input clock signal, from the input clock signal and a signal obtained by delaying the input clock signal; and an A/D conversion unit configured to perform A/D conversion on an input analog signal using the multi-phase clock signals generated by the phase-difference clock generation unit.

A/D conversion device, gray code generation device, signal processing device, imaging element, and electronic device

To inhibit a decrease in inductance of an inductor in a plurality of semiconductor chips that are stacked. A semiconductor device includes: first and second semiconductor chips that are stacked; a first inductor; an arrangement-restricted region; and a circuit. In the semiconductor device, the first inductor is arranged in the first semiconductor chip. The arrangement-restricted region is provided in a region of the second semiconductor chip corresponding to the first inductor. The circuit is arranged in a region of the second semiconductor chip not corresponding to the arrangement-restricted region.

Semiconductor device, semiconductor chip, and system

A three-phase transmitter that sets voltages of first, second, and third output terminals based on first, second, and third signals. The transmitter includes a first transmitting section configured to set the voltage of the first output terminal based on the first and third signals; a second transmitting section configured to set the voltage of the second output terminal based on the first and second signals; and a third transmitting section configured to set the voltage of the third output terminal based on the second and third signals.

Growing community of inventors

Tokyo, Japan

Takanori Saeki