Rohm Co., Ltd.

Takanori Ozawa

Noriyuki Shimoji

Takaaki Fuchikami

Hironobu Nakao

Hidemi Takasu

Hiromitsu Kimura

Hiroaki Ito

Masataka Tsuruta

Izumi Yano

Toshiyuki Shiraishi

A nonvolatile logic cell (nonvolatile storage element)includes ferroelectric capacitorsand MOSFETs. A plurality of ferroelectric dummy capacitorsandare formed in a periphery of the nonvolatile logic cell. Each of the ferroelectric capacitorsand the ferroelectric dummy capacitorsandincludes a lower electrode, a ferroelectric filmformed above the lower electrode, and an upper electrodeformed above the ferroelectric film

Ferroelectric memory array surrounded by ferroelectric dummy capacitors

Provided is a semiconductor device that has a low interface resistance between a contact plug and a bottom electrode of a real ferroelectric capacitor. A real capacitor oxidation suppression structure ST including a dummy ferroelectric capacitorand a second plugis formed. The dummy ferroelectric capacitorincludes a second bottom electrode, a second ferroelectric film, and a second top electrode, and is not used as a nonvolatile memory element. The second bottom electrodeis formed on an interlayer insulating film. The second ferroelectric filmis formed on the second bottom electrode. The second top electrodeis formed on the second ferroelectric film. The second plugpenetrates the interlayer insulating filmand electrically connects the second bottom electrodeto a semiconductor substrate

Semiconductor device

A data holding devicehas an inverter loop, a differential pair circuitconnected to the ground terminals of inverters, a first potential setterconfigured to turn the output terminals of the inverters to a first potential (VDD), and a second potential setterconfigured to turn the ground terminals of the inverters to a second potential (VSS). During data holding, the differential pair circuitand the first potential setterare disabled so that the ground terminals of the inverters are at the second potential. During data writing, the differential pair circuitis disabled so that the output terminal of one inverter is at the first potential and the ground terminal of the other inverter is at the second potential.

Data holding device, nonvolatile data holding device, and data reading method

A data memory device is provided that is capable of reading data accurately even if the reading action is repeated. Respective output ends of memory cells D -D and input ends on one side of respective exclusive OR elements Eo -Eo are interconnected, and the output end of a polarity holding cell Dc and the input ends on the other side of the respective exclusive OR elements Eo -Eo are interconnected. When it is assumed that the stored value of the memory cell D is a logic &ldquo;1&rdquo; and the stored value of the polarity holding cell Dc is a logic &ldquo;0,&rdquo; the value of the output data Do read out becomes a logic &ldquo;1&rdquo;. By the reversal writing action that follows, the value of the memory cell D becomes a logic &ldquo;0&rdquo; and the stored value of the polarity holding cell Dc becomes a logic &ldquo;1.&rdquo; When the value of the memory cell D is read again in that state, the value of the output data Do is still a logic &ldquo;1.&rdquo; That is to say, even if data reading action is repeated, values of the output data Do -Do remain unchanged. However, the direction of polarization of respective ferroelectric capacitors constituting the memory cells D -D and the polarity holding cell Dc are reversed every time of the reading.

Data memory device

A semiconductor memory device including a memory element for storing data, and a supplemental element substantially electrically associated with the memory element at least at the time of reading data. The semiconductor memory device is for reading data stored in the memory element by applying specified electric action to the compound element including the memory element and the supplemental element substantially electrically mutually associated. The semiconductor memory device is characterized in that the electric characteristic of the supplemental element is adapted to be variable based on a signal for changing the electric characteristic of the supplemental element so that data may be read free from troubles.

Semiconductor memory device having a supplemental element for reading data stored in a memory element

A nonvolatile semiconductor memory which includes a voltage supply terminal, a multiplicity of memory cells, a voltage selection circuit, and a voltage dropping circuit. The terminal receives a supply voltage from an external voltage source. The voltage selection circuit is coupled to the terminal for selectively outputting a first and a second voltage to be supplied to the memory cells. The voltage dropping circuit is coupled between the voltage selection circuit and the memory cells for dropping the second voltage output from the voltage selection circuit before it is input to the memory cells.

Nonvolatile semiconductor memory having a voltage selection circuit

In a ferroelectric memory and a method of manufacturing it, a metallic layer,of Ni, which is silicified at a temperature lower than the temperature when a ferroelectric layer FL looses ferroelectricity non-reversibly, is formed so as to be partially brought into contact with the upper surface of one of the source/drain regions,. Thereafter, the metallic layer,is; heated at the temperature lower than the temperature when the ferroelectric layer FL looses the ferroelectricity non-reversibly. Thus, the metallic layer,is silicified to form a silicide layer,. Therefore, without deteriorating the function of the ferroelectric layer FL, the portion of the metallic layer,which is contact with the upper surface of the source/drain region,can be sufficiently silicified. Ni has a very weak reduction/catalysis function for the ferroelectric layer FL. Therefore, the metallic layer,not silicified does not adversely affect the ferroelectric layer FL in the post manufacturing steps. Thus, the semiconductor device can give a small connection resistance between a silicon layer and a wiring layer while holding the function of a ferroelectric layer.

Semiconductor device and method of manufacturing the same

A nonvolatile memory element capable of using desired ferroelectric materials, exhibiting a high reliability and performing processings such as reading of information without destruction of stored contents is provided. A memory cell comprises two capacitors Cf1 and Cf2 connected to each other in series. Both capacitors are ferroelectric capacitors manufactured by the same steps. Accordingly, the coupling ratio between both capacitors can be changed by only the change of surface areas thereof. A voltage corresponding to the information to be stored is applied to the opposite ends of the memory cell 20 to cause polarization reversal and as a result, the information is written thereinto. In order to read the stored information, a ground potential is applied to the opposite ends of the memory cell 20. On the basis of the potential generated at a connection 20c upon the application of the ground potential, the information can be read.

Ferroelectric nonvolatile memory element having capacitors of same

A non-volatile semiconductor memory includes a ferroelectric memory cell 3 and a voltage detection circuit 2. The voltage detecting circuit 2 monitors the drop of a power supply voltage and cuts off the power supply voltage when it is lower than a prescribed voltage so that the memory cell 3 is not operated. In addition, in response to a control input signal, a control circuit 1 is provided to control the power supply voltage so that it is not cut off even when it is lower than the prescribed voltage. In this configuration, the non-volatile semiconductor memory device can be sufficiently subjected to the screening test for a short time without suffering from stress for a long time.

Non-volatile semiconductor memory device and its testing method

The present invention relates to a structure of semiconductor chip joint for mounting a plurality of semiconductor chips onto a single package. The joint comprises two or more semiconductor chips, the chips each having an element formation surface and a rear surface and being piled up with their element formation surfaces directed either in a first direction or in a second direction by turns so that their element formation surfaces are opposed to each other while their rear surfaces are opposed to each other, a bonding pad provided on the element formation surface of the chip directed in the first direction, connecting pad provided on the element formation surface of the chip directed both in the first direction and in the second direction;

Semiconductor device with stacked alternate-facing chips

A method for making a nonvolatile memory device having a field effect transistor for storing information, and a Schottky diode in series with the field effect transistor. The field effect transistor includes source and drain regions in a semiconductor substrate, with a channel region interposed between them and a gate electrode above the channel region. A ferroelectric gate film is sandwiched between the channel region and the gate electrode. In the method, a conductive barrier meterial is deposited in contact with the source region of the field effect transistor to make the Schottky diode. In reading information from the memory device, voltage is applied to a serial circuit consisting of the field effect transistor and the Schottky diode to turn the Schottky diode on.

Method for making a nonvolatile memory device utilizing a field effect

A semiconductor device having a source region, a drain region, a channel region between the source region and the drain region, a gate consisting of at least three input electrodes provided above the channel region, and a potential modulating film provided between the channel region and the gate. The potential modulating film can assume at least two potential modulating states, so that the potential of the channel region is modulated between and held at different values. The potential of the channel region is modulated by changing the state of the potential modulating film. Specifically, the potential of the channel region is modulated by not only applying voltages to the input electrodes but also controlling the state of the potential modulating film. If in processing at least three input signals, a predetermined one of them corresponds to control of the state of the potential modulating film and the remaining input signals correspond to the input voltages to the input electrodes, the number of wires can be decreased.

Semiconductor device and method for processing multiple input signals

A pair of impurity regions are formed at a specified interval in a semiconductor substrate. A channel region is defined between the impurity regions. A select gate is provided on the channel region, and a sidewall for holding electric charge is provided along a side of the select gate. A tunnel insulating film is interposed between the sidewall for holding electric charge and the channel region. An insulating film covers the sidewall for holding electric charge. A control gate is provided on the insulating film lying over the sidewall. In such a structure, since the select gate can have a large cross-sectional area, speed-up of the reading can be attained.

Nonvolatile semiconductor memory device

A drain diffusion layer acting as a drain of both of a memory transistor and a selection transistor, and a source diffusion layer acting as a source of both of the memory transistor and the selection transistor are formed in a semiconductor substrate. A floating gate having a convex upper surface is formed on a tunnel insulating film in the vicinity of the drain diffusion layer. A common gate acting both as a control gate of the memory transistor and as a gate of the selection transistor is formed such that its one end is located over the floating gate and the other end is located in the vicinity of the source diffusion layer.

Nonvolatile semiconductor memory device and manufacturing method therefor

In the non-volatile semiconductor memory device according to the present invention, a floating gate is provided on a channel region which is interposed between a source region and a drain region through a tunnel insulation film. The tunnel insulation film and the floating gate are formed spaced apart from the source region by a predetermined offset distance. A sidewall gate which is insulated from the channel region and the floating gate is provided in an offset distance portion on the channel region. An offset region immediately under the sidewall gate functions as an inversion layer, thereby to make it possible to read out information at high speed utilizing the inversion of the offset region.

Growing community of inventors

Kyoto, Japan

Takanori Ozawa