Nec Corporation

Takanori Nishi

Katsumi Kikuchi

Akira Miyata

Suguru Watanabe

Hideyuki Satou

Kenji Nanba

Ayami Yamaguchi

Shigeyuki Iwasa

Tsuyoshi Yamamoto

Yoshihito Hashimoto

Tomohiro Yamaji

Kenji Kobayashi

Katsumi Maeda

Kentaro Nakahara

Hiroshi Kajitani

Takashi Manako

Hidekazu Kimura

Shoji Sekino

Yoichi Shimizu

Terumasa Shimoyama

Haruyuki Yoshigahara

Provided is a quantum device capable of suppressing reduction in performance of quantum bit even when a quantum chip is flip-chip mounted on an interposer. A quantum chip () is flip-chip mounted on an interposer () by a bump (). A coplanar line () coupling adjacent quantum bits is formed on the quantum chip (). A gap () is provided, in the interposer (), at a location facing a center conductor () of the coplanar line (). A second ground electrode () is formed around gap (). The interposer () has a connection electrode () connecting the second ground electrode () around the gap (). A bump (A) formed in the vicinity of the connection electrode () is connected to the first ground electrode () and the second ground electrode ().

Quantum device and quantum computer

Provided are an oscillator and a quantum computer capable of suppressing an occupied area of a circuit. An oscillator () includes a resonator () including a plurality of loop circuits in which a first superconducting line (), a first Josephson junction (), a second superconducting line (), and a second Josephson junction () are annularly connected, and a magnetic field application circuit () including an electrode that goes around in a predetermined shape and configured to apply a magnetic field to the loop circuit, in which the electrode is arranged so as to face at least two of the loop circuits.

Oscillator and quantum computer

A quantum device according to an example embodiment includes: a quantum chip with a first surface and a second surface located on a side opposite to the first surface, in the quantum chip, at least a part of a qubit circuit being provided on the second surface; a first interposer with a third surface and a fourth surface located on a side opposite to the third surface, the first interposer being connected to the quantum chip in such a manner that the second surface of the quantum chip is opposed to the third surface of the first interposer; and a second interposer with a fifth surface and a sixth surface located on a side opposite to the fifth surface, the second interposer being connected to the first interposer in such a manner that the fourth surface of the first interpose is opposed to the fifth surface of the second interposer.

Quantum device

A quantum device capable of securing terminals for external connection is provided. A quantum device according to an example embodiment includes a quantum chip, an interposeron which the quantum chipis mounted, and a socketdisposed so as to be opposed to the interposer, the socketcomprising a movable pinand a housingsupporting the movable pin, in which at least one end of the movable pin, which includes the one end and the other end opposite to the one end, is movable relative to the housing, the one end being in electrical contact with a terminal of the interposer, and the other end is in an electrical contact with a terminal of a boardon which a connectoris formed, the connectorbeing configured to serve as an external input/output.

A quantum device capable of improving a cooling effect while securing the number of terminals is provided. A quantum device according to an example embodiment includes a quantum chip, and an interposeron which the quantum chipis mounted, in which the interposerincludes a conductive wiring line CLelectrically connected to the quantum chip, and a metal filmdisposed in a part of the interposerthat is in contact with a sample stagehaving a cooling function, and a mounting surfaceof the interposeron which the quantum chipis mounted or an opposite surfaceopposite to the mounting surfaceincludes a first area ARand a second area ARdifferent from the first area ARas viewed in a direction perpendicular to the mounting surfaceor the opposite surface

Quantum device having quantum chip on interposer in contact with sample stage

A quantum device () includes: an interposer (); a quantum chip (); a first connection part () that is provided between the interposer () and the quantum chip () and electrically connects a wiring layer of the interposer () to a wiring layer of the quantum chip (); and a second connection part () that is provided on a main surface of the interposer () where the first connection part () is arranged and is connected to a cooling plate ().

Quantum device and method of manufacturing the same

A quantum device according to an example embodiment includes a quantum chip, and an interposeron which the quantum chipis mounted, in which the interposerincludes a conductive wiring line CLelectrically connected to the quantum chip, a mounting surfaceof the interposeron which the quantum chipis mounted or an opposite surfaceopposite to the mounting surfaceincludes a first area ARand a second area ARdifferent from the first area ARas viewed in a direction perpendicular to the mounting surfaceor the opposite surface, the conductive wiring line CLis disposed in the first area ARon the mounting surfaceor the opposite surface, and a movable memberis in contact with the second area ARof the interposer

A quantum device () includes an interposer (), a quantum chip () mounted on the interposer (), and a shield part () provided so as to surround a quantum circuit region of the interposer () and the quantum chip (). Accordingly, the quantum device () is able to prevent interference in the quantum circuit region due to exogenous noise.

Quantum device including shield part and method of manufacturing the same

A quantum device () includes: an interposer (); a quantum chip (); and a connection part () that is provided between the interposer () and the quantum chip () and electrically connects a wiring layer of the interposer () to a wiring layer of the quantum chip (), in which the connection part () includes: a plurality of pillars () arranged on a main surface of the interposer (); and a metal film () provided on a surface of the plurality of pillars () in such a way that it contacts the wiring layer of the quantum chip () and the thickness of the metal film at outer peripheral parts of the tip of each of the plurality of pillars () becomes larger than the thickness of the metal film at a center part of the tip of each of the plurality of pillars ().

A secondary battery exhibiting high charge and discharge rate characteristics can be provided, by making the secondary battery have a cathode including a nitroxyl compound taking a nitroxyl cation substructure represented by the following formula (1) in an oxidized state and a nitroxyl radical substructure represented by the following formula (2) in a reduced state, an anode including an active material capable of reversibly intercalating and deintercalating a lithium ion, and an electrolyte solution including a lithium salt and an aprotic organic solvent, and employing Li[(FSO)N] as the lithium salt: 

Power storage device

A non-aqueous secondary battery includes: a positive-electrode collector layer; a positive-electrode layer formed on one surface of the positive-electrode collector layer; a negative-electrode collector layer; a negative-electrode layer formed on one surface of the negative-electrode collector layer so as to be opposed to the positive-electrode layer; a separator provided between the positive-electrode layer and the negative-electrode layer; and a positive-electrode-side insulating layer and a negative-electrode-side insulating layer respectively formed on another surface of the positive-electrode collector layer and another surface of the negative-electrode collector layer. Circumferential inner surfaces of peripheral edges of the positive-electrode collector layer and the negative-electrode collector layer are joined with a sealing agent including at least a positive-electrode fusion layer, a gas barrier layer, and a negative-electrode fusion layer. The positive-electrode-side insulating layer and/or the negative-electrode-side insulating layer has a battery-side recess provided on a surface.

Non-aqueous secondary battery, mounted unit, and method for manufacturing non-aqueous secondary battery

A polymer electrolyte fuel cell includes a power generation part as an electrolyte membrane-electrode assembly formed of a solid polymer electrolyte membrane, a fuel electrode arranged in contact with one side of the solid polymer electrolyte membrane and an oxygen electrode arranged in contact with the other side of the membrane, and a fuel supply part for storing and supplying an alcohol fuel to the fuel electrode. The fuel supply part is composed of a high-concentration fuel tank for storing and supplying a highly-concentrated fuel and a water fuel tank for storing and supplying a water fuel. The fuel is gasified and supplied to the power generation part through a fuel gasification/supply layer provided between at least the high-concentration fuel tank and the fuel electrode.

Polymer electrolyte fuel cell

A fuel cell system includes: a fuel cell stack configured to have a plurality of unit fuel cells arranged on an identical plane; a chassis configured to cover at least one side of said fuel cell stack via an air flow space; and a condensation water holding member configured to be provided in at least a part between said fuel cell stack and said chassis, have a mesh shape and have a function for keeping moisture.

Growing community of inventors

Tokyo, Japan

Takanori Nishi