Fujitsu Corporation

Takanori Nawa

Kenji Suzuki

Hiroyuki Yamamoto

Toru Osajima

Takashi Yoneda

Koji Banno

Hideji Sumi

Eiji Fujine

Kazushige Itazu

Masuo Inui

Masahito Isoda

Takayuki Matsuzawa

Hiroshi Yuyama

Naomi Mori

Koji Tsuneto

In a higher layer, power source wiring is provisionally provided between a logic-decided functional block and the logic-undecided functional block. Then, a resistor network of the power source wiring within the logic-undecided functional block is prepared by assuming that a current source has been connected to a power source terminal of the logic-undecided functional block. A resistor network of a total power source wiring in the higher layer is prepared by using this local resistor network. An optimum width of the power source wiring is determined by analyzing this resistor network. Based on the width, the power source wiring of the higher layer is rewired.

Method of designing wiring for power sources in a semiconductor chip, and a computer product

A program for generating layout data for a semiconductor integrated circuit analyzes a power network of individual modules in order to determine when an iterative layout process is complete. First, the individual modules are laid out and power supply wirings to the modules are laid out. Next, using cell size information about the cells within each of the modules, the cells of each module are temporarily arranged within the modules. Then, the power wirings and power supply terminals for each module are specified. A power network of each module is then sampled based on the cells, power wirings and power supply terminals of each module. Using the sample data, it is determined whether the modules and the power supply wirings to the modules need to be laid out again. The program may be executed on a CAD system.

Method and apparatus to optimize power wiring layout and generate wiring layout data for a semiconductor integrated circuit

A design method optimizes the dimensions (length and width) of power supply lines in a semiconductor integrated circuit. First, the power supply lines are analyzed to determine initial values for the lines. Then, a current-capacitance ratio of each of the power supply lines is calculated using the analysis results. Finally, a dimension of each of the poser supply lines is computed so that the corresponding current-capacitance ratio is within a predetermined range. The resulting power supply lines are as narrow as possible without causing a voltage drop violation or a current amount violation.

Method for optimizing power supply wiring in a semiconductor integrated circuit

A method and apparatus for generating external power wiring layout data for a semiconductor integrated circuit device determines an optimum layout without performing time consuming circuit simulation. An external power wiring supplies power to each of the functional blocks of the device. Design information is used to calculate a current consumption ratio for each power supply terminal of each functional block. Then, the current consumption for each power supply terminal is calculated using the calculated current consumption ratios. An external power wiring network is generated based on the calculated current consumption for each terminal. The generated external power wiring network is then analyzed and voltage and current values for each part of the network are calculated. Using the calculated voltage and current values, the wires are then optimally sized.

Method and apparatus for generating layout data for a semiconductor integrated circuit device

A semiconductor integrated circuit includes an emitter-coupled logic circuit coupled between a first power source line and a second power source line. The emitter-coupled logic circuit has a differential circuit and an output buffer circuit. A wiring line is provided which is coupled to the emitter of a first transistor of the output buffer circuit and which carries an output signal of the emitter-coupled logic circuit to a circuit of the next stage. The semiconductor integrated circuit also includes a second transistor having an emitter coupled to the emitter of the first transistor, a collector coupled to the first power source line, and a base supplied with a second reference voltage, and a constant-current source coupled to the emitter of the first and second transistors and allowing a constant current to selectively pass through either the first transistor or the second transistor. A current switching circuit is formed by the first and second transistors and the constant-current source, and the constant current passes through either the first transistor or the second transistor on the basis of a potential of the base of the first transistor and the second reference voltage applied to the base of the second transistor.

Semiconductor integrated circuit having ECL circuits and a circuit for

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Kasugai, Japan

Takanori Nawa